SLUS694G March   2006  – December 2014

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-Path Management
        1. 8.3.1.1 Case 1: IN Mode (Mode = High)
          1. 8.3.1.1.1 System Power
          2. 8.3.1.1.2 Charge Control
          3. 8.3.1.1.3 Dynamic Power-Path Management (DPPM)
        2. 8.3.1.2 Case 2: USB Mode (Mode = L)
          1. 8.3.1.2.1 System Power
          2. 8.3.1.2.2 Charge Control
          3. 8.3.1.2.3 Dynamic Power-Path Management (DPPM)
          4. 8.3.1.2.4 Application Curve Descriptions
      2. 8.3.2 Battery Temperature Monitoring
      3. 8.3.3 Charge Status Outputs
      4. 8.3.4 PG, Outputs (Power Good)
      5. 8.3.5 Short-Circuit Recovery
      6. 8.3.6 VREF
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode - V(IN) < VI(BAT)
      2. 8.4.2 Standy Mode - V(IN) > VI(BAT)and CE (Chip Enable) Pin = Low
      3. 8.4.3 Battery Charge Mode - V(IN) > VI(BAT), Battery Present, CE pin = High and DPPM Pin Not Floating
        1. 8.4.3.1 Automous Power Selection and Boot-Up Sequence
        2. 8.4.3.2 Charge Control
        3. 8.4.3.3 Battery Preconditioning
        4. 8.4.3.4 Battery Charge Current
        5. 8.4.3.5 Battery Voltage Regulation
        6. 8.4.3.6 Temperature Regulation and Thermal Protection
        7. 8.4.3.7 Charge Timer Operation
        8. 8.4.3.8 Timer Fault Recovery
        9. 8.4.3.9 Charge Termination and Recharge
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Input and Output Capacitors
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHL|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Input voltage IN (DC voltage with respect to VSS) –0.3 18 V
Input voltage BAT, CE, DPPM, PG, Mode, OUT, ISET1, ISET2, STAT1, STAT2, TS, (all DC voltages with respect to VSS) –0.3 7
VREF (DC voltage with respect to VSS) –0.3 VO(OUT) + 0.3
TMR –0.3 VO + 0.3
Input current 3.5 A
Output current OUT 4
BAT(2) –4 3.5
Output source current (in regulation at 3.3-V VREF) VREF 30 mA
Output sink current PG, STAT1, STAT2, 15 mA
Junction temperature, TJ –40 150 °C
Lead temperature (soldering, 10 s) 300
Storage temperature, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted.
(2) Negative current is defined as current flowing into the BAT pin.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±XXX V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±YYY V may actually have higher performance.

7.3 Recommended Operating Conditions

MIN MAX UNIT
VCC Supply voltage (VIN) (1) 4.35 16 V
IIN Input current 2 A
TJ Operating junction temperature range –40 125 °C
(1) Verify that power dissipation and junction temperatures are within limits at maximum VCC .

7.4 Thermal Information

THERMAL METRIC(1) bq2407x UNIT
RHL
20 PINS
RθJA Junction-to-ambient thermal resistance 40.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 42.0
RθJB Junction-to-board thermal resistance 16.6
ψJT Junction-to-top characterization parameter 0.7
ψJB Junction-to-board characterization parameter 16.6
RθJC(bot) Junction-to-case (bottom) thermal resistance 4.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over junction temperature range (0°C ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT BIAS CURRENTS
ICC(SPLY) Active supply current, VCC VVCC > VVCC(min) 1 2 mA
ICC(SLP) Sleep current (current into BAT pin) VIN < V(BAT)
2.6 V ≤ VI(BAT) ≤ VO(BAT-REG),
Excludes load on OUT pin		 2 5 μA
ICC(IN-STDBY) Input standby current VI(IN) ≤ 6V, Total current into IN pin with chip disabled, Excludes all loads, CE=LOW, after t(CE-HOLDOFF) delay 200
ICC(BAT-STDBY) BAT standby current Total current into BAT pin with input present and chip disabled;
Excludes all loads, CE=LOW,
after t(CE-HOLDOFF) delay,
0°C ≤ TJ ≤ 85°C(1)		 45 65
IIB(BAT) Charge done current, BAT Charge DONE, input supplying the load 1 5
OUT PIN-VOLTAGE REGULATION
VO(OUT-REG) Output regulation
voltage		 bq24070 VI(IN) ≥ 4.4 V + VDO 4.4 4.5 V
bq24071 VI(IN) ≥ 6 V + VDO 6.0 6.3
OUT PIN – DPPM REGULATION
V(DPPM-SET) DPPM set point(4) VDPPM-SET < VOUT 2.6 3.8 V
I(DPPM-SET) DPPM current source Input present 95 100 105 μA
SF DPPM scale factor V(DPPM-REG) = V(DPPM-SET) × SF 1.139 1.150 1.162
OUT PIN – FET (Q1, Q2) DROP-OUT VOLTAGE RDS(on))
V(INDO) IN-to-OUT dropout voltage(5) VI(IN) ≥ VCC(min), Mode = High,
II(IN) = 1 A, (IO(OUT)+ IO(BAT)), or no input		 300 475 mV
V(BATDO) BAT-to-OUT dropout voltage (discharging) VI (BAT) ≥ 3 V, II(BAT)= 1.0 A, VCC < VI(BAT) 40 100
OUT PIN - BATTERY SUPPLEMENT MODE
VBSUP1 Enter battery supplement mode (battery supplements OUT current in the presence of input source VI(BAT)> 2 V VI(OUT)
≤ VI(BAT) 
– 60 mV		 V
VBSUP2 Exit battery supplement mode VI(BAT)> 2 V VI(OUT)
≥ VI(BAT) 
– 20 mV
OUT PIN - SHORT CIRCUIT
IOSH1 BAT to OUT short-circuit recovery Current source between BAT to OUT for short-circuit recovery to
VI(OUT) ≤ VI(BAT) –200 mV 		10 mA
RSHIN IN to OUT short-circuit limit VI(OUT)  ≤ 1 V 500 Ω
BAT PIN CHARGING – PRECHARGE
V(LOWV) Precharge to fast-charge transition threshold Voltage on BAT 2.9 3 3.1 V
TDGL(F) Deglitch time for fast-charge to precharge transition(9) tFALL = 100 ns, 10 mV overdrive,
VI(BAT) decreasing below threshold		 22.5 ms
IO(PRECHG) Precharge range 1 V < VI(BAT) < V(LOWV), t < t(PRECHG),
IO(PRECHG) = (K(SET) × V(PRECHG))/ RSET		 10 150 mA
V(PRECHG) Precharge set voltage 1 V < VI(BAT) < V(LOWV), t < t(PRECHG) 225 250 275 mV
BAT PIN CHARGING - CURRENT REGULATION
IO(BAT) Battery charge current range(6) VI (BAT) > V(LOWV), Mode = High
IOUT(BAT) = (K(SET) × V(SET) / RSET),
VI(OUT) > VO(OUT-REG) + V(DO-MAX)		 100 1000 1500 mA
RPBAT BAT to OUT pullup VI (BAT)< 1 V 1000 Ω
V(SET) Battery charge current set voltage(7) Voltage on ISET1, VVCC ≥ 4.35 V,
VI(OUT)- VI(BAT) > V(DO-MAX),
VI(BAT) > V(LOWV)		 2.47 2.50 2.53 V
K(SET) Charge current set factor, BAT 100 mA ≤ IO(BAT) ≤ 1.5 A 375 425 450
10 mA ≤ IO(BAT) ≤ 100 mA(8) 300 450 600
USB MODE INPUT CURRENT LIMIT
I(USB) USB input port current range ISET2 = Low 80 90 100 mA
ISET2 = High 400 500
BAT PIN CHARGING VOLTAGE REGULATION, VO (BAT-REG) + V (DO-MAX) < VCC, ITERM < IBAT(OUT) ≤ 1 A
VO(BAT-REG) Battery charge voltage 4.2 V
Battery charge voltage regulation accuracy TA = 25°C –0.5% 0.5%
–1% 1%
CHARGE TERMINATION DETECTION
I(TERM) Charge termination detection range VI(BAT) > V(RCH),
I(TERM) = (K(SET) × V(TERM))/ RSET		 10 150 mA
V(TERM) Charge termination set voltage, measured on ISET1 VI(BAT) > V(RCH) , Mode = High 230 250 270 mV
VI(BAT) > V(RCH) , Mode = Low 95 100 130
TDGL(TERM) Deglitch time for termination detection tFALL = 100 ns, 10 mV overdrive,
ICHG increasing above or decreasing below threshold 		22.5 ms
TEMPERATURE SENSE COMPARATORS
VLTF High voltage threshold Temp fault at V(TS) > VLTF 2.465 2.500 2.535 V
VHTF Low voltage threshold Temp fault at V(TS) < VHTF 0.485 0.500 0.515 V
ITS Temperature sense current source 94 100 106 μA
TDGL(TF) Deglitch time for temperature fault detection(9) R(TMR) = 50 kΩ, VI(BAT) increasing or
decreasing above and below;
100-ns fall time, 10-mv overdrive		 22.5 ms
BATTERY RECHARGE THRESHOLD
VRCH Recharge threshold voltage VO(BAT-REG)
–0.075		 VO(BAT-REG)
–0.100		 VO(BAT-REG)
–0.125		 V
TDGL(RCH) Deglitch time for recharge detection(9) R(TMR) = 50 kΩ, VI(BAT) increasing
or decreasing below threshold,
100-ns fall time, 10-mv overdrive		 22.5 ms
STAT1, STAT2, AND PG, OPEN-DRAIN (OD) OUTPUTS(11)
VOL Low-level output saturation voltage IOL = 5 mA, An external pullup
resistor ≥ 1 K required.		 0.25 V
ILKG Input leakage current 1 5 μA
ISET2, CE INPUTS
VIL Low-level input voltage 0 0.4 V
VIH High-level input voltage 1.4
IIL Low-level input current, CE –1 μA
IIH High-level input current, CE 1
IIL Low-level input current, ISET2 VISET2 = 0.4 V –20
IIH High-level input current, ISET2 VISET2 = VCC 40
t(CE-HLDOFF) Holdoff time, CE CE going low only 3.3 6.2 ms
MODE INPUT
VIL Low-level input voltage Falling Hi→Low; 280 K ± 10% applied when low. 0.975 1 1.025 V
VIH High-level input voltage Input RMode sets external hysteresis VIL + .01 VIL + .024 V
IIL Low-level input current, Mode –1 μA
TIMERS
K(TMR) Timer set factor t(CHG) = K(TMR) × R(TMR) 0.313 0.360 0.414 s/Ω
R(TMR)(10) External resistor limits 30 100 kΩ
t(PRECHG) Precharge timer 0.09 × t(CHG) 0.10 × t(CHG) 0.11 × t(CHG) s
I(FAULT) Timer fault recovery pullup from OUT to BAT 1 kΩ
CHARGER SLEEP THRESHOLDS (PG THRESHOLDS, LOW → POWER GOOD)
V(SLPENT)(14) Sleep-mode entry threshold V(UVLO) ≤ VI(BAT) ≤ VO(BAT-REG),
No t(BOOT-UP) delay		 VVCC ≤
VI(BAT)
+125 mV		 V
V(SLPEXIT)(14) Sleep-mode exit threshold V(UVLO) ≤ VI(BAT) ≤ VO(BAT-REG),
No t(BOOT-UP) delay		 VVCC ≥
VI(BAT)
+190 mV
t(DEGL) Deglitch time for sleep mode(12) R(TMR) = 50 kΩ,
V(IN) decreasing below threshold, 100-ns fall time, 10-mv overdrive		 22.5 ms
START-UP CONTROL BOOT-UP
t(BOOT-UP) Boot-up time On the first application of input with Mode Low 120 150 180 ms
SWITCHING POWER SOURCE TIMING
tSW-BAT Switching power source from input to battery When input applied. Measure from:
[PG: Lo → Hi to I(IN) > 5 mA],
I(OUT) = 100 mA,
RTRM = 50 K		 50 μs
THERMAL SHUTDOWN REGULATION(13)
T(SHTDWN) Temperature trip TJ (Q1 and Q3 only) 155 °C
Thermal hysteresis TJ (Q1 and Q3 only) 30
TJ(REG) Temperature regulation limit TJ (Q2) 115 135
UVLO
V(UVLO) Undervoltage lockout Decreasing VCC 2.45 2.50 2.65 V
Hysteresis 27 mV
VREF OUTPUT
VO(VREF) Output regulation voltage Active only if IN or USB is present,
VI(OUT) ≥ VO(VREF) + (IO(VREF) × RDS(on)) 		3.3 V
Regulation accuracy(2) –5% 5%
IO(VREF) Output current 20 mA
RDS(on) On resistance OUT to VREF 50 Ω
C(OUT)(3) Output capacitance 1 μF
(1) This includes the quiescent current for the integrated LDO.
(2) In standby mode (CE low) the accuracy is ±10%.
(3) VREF output capacitor not required, but one with a value of 0.1 μF is recommended.
(4) V(DPPM-SET) is scaled up by the scale factor for controlling the output voltage V(DPPM-REG).
(5) VDO(max), dropout voltage is a function of the FET, RDS(on), and drain current. The dropout voltage increases proportionally to the increase in current.
(6) When input current remains below 2 A, the battery charging current may be raised until the thermal regulation limits the charge current.
(7) For half-charge rate, V(SET) is 1.25 V ± 25 mV.
(8) Specification is for monitoring charge current through the ISET1 pin during voltage regulation mode, not for a reduced fast-charge level.
(9) All deglitch periods are a function of the timer setting and is modified in DPPM or thermal regulation modes by the percentages that the program current is reduced.
(10) To disable the fast-charge safety timer and charge termination, tie TMR to the VREF pin. Tying the TMR pin high changes the timing resistor from the external value to an internal 50 kΩ ±25%, which can add an additional tolerance to any timed specification. The TMR pin normally regulates to 2.5 V when the charge current is not restricted by the DPPM or thermal feedback loops. If these loops become active, the TMR pin voltage will be reduced proportionally to the reduction in charge current and the clock frequency will be reduced by the same percentage (timed durations will count down slower, extending their time). The TMR pin is clamped at 0.80 V, for a maximum time extension of 2.5 V ÷ 0.8 V × 100 = 310%.
(11) See Charger Sleep mode for PG (VCC = VIN) specifications.
(12) Does not declare sleep mode until after the deglitch time and implement the needed power transfer immediately according to the switching specification.
(13) Reaching thermal regulation reduces the charging current. Battery supplement current is not restricted by either thermal regulation or shutdown. Input power FETs turn off during thermal shutdown. The battery FET is only protected by a short-circuit limit which typically does not cause a thermal shutdown (input FETs turning off) by itself.
(14) The IC is considered in sleep mode when IN is absent (PG = OPEN DRAIN).

7.6 Typical Characteristics

sigma_lus694.gifFigure 1. SIGMA Typical OUT Voltage Regulation, bq24070