The bqSWITCHER™ series are highly integrated Li-ion and Li-polymer switch-mode charge management devices targeted at a wide range of portable applications. The bqSWITCHER™ series offers integrated synchronous PWM controller and power FETs, high-accuracy current and voltage regulation, charge preconditioning, charge status, and charge termination, in a small, thermally enhanced VQFN package. The system-controlled version provides additional inputs for full charge management under system control.
The bqSWITCHER™ charges the battery in three phases: conditioning, constant current, and constant voltage. Charge is terminated based on user- selectable minimum current level. A programmable charge timer provides a safety backup for charge termination. The bqSWITCHER™ automatically restarts the charge cycle if the battery voltage falls below an internal threshold. The bqSWITCHER™ automatically enters sleep mode when VCC supply is removed.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
bq241xx | VQFN (20) | 3.50 mm × 4.50 mm |
Changes from O Revision (March 2010) to P Revision
Changes from M Revision (August 2008) to N Revision
Changes from L Revision (December 2007) to M Revision
Changes from K Revision (November 2007) to L Revision
Changes from J Revision (October 2007) to K Revision
Changes from I Revision (August 2007) to J Revision
Changes from H Revision (July 2007) to I Revision
Changes from G Revision (June 2007) to H Revision
Changes from F Revision (January 2007) to G Revision
CHARGE REGULATION VOLTAGE (V) | INTENDED APPLICATION | PART NUMBER (1) (2) (3) |
---|---|---|
4.2 V | Stand-alone | bq24100 |
1 or 2 cells selectable (CELLS pin, 4.2 V or 8.4 V) | Stand-alone | bq24103 |
1 or 2 cells selectable (CELLS pin, 4.2 V or 8.4 V) | Stand-alone | bq24103A |
1 or 2 cells selectable (CELLS pin, 4.2 V or 8.4 V) (Blinking status pins) |
Stand-alone | bq24104 |
Externally programmable (2.1 V to 15.5 V) | Stand-alone | bq24105 |
4.2 V (Blinking status pins) | Stand-alone | bq24108 |
bq24109 | ||
1 or 2 cells selectable (CELLS pin, 4.2 V or 8.4 V) | System-controlled | bq24113 |
1 or 2 cells selectable (CELLS pin, 4.2 V or 8.4 V) | System-controlled | bq24113A |
Externally programmable (2.1 V to 15.5 V) | System-controlled | bq24115 |
PIN | I/O | DESCRIPTION | |||||
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NAME | bq24100, bq24108, bq24109 |
bq24103, bq24103A bq24104 |
bq24105 | bq24113, bq24113A | bq24115 | ||
BAT | 14 | 14 | 14 | 14 | 14 | I | Battery voltage sense input. Bypass it with a 0.1 μF capacitor to PGND if there are long inductive leads to battery. |
CE | 16 | 16 | 16 | 16 | 16 | I | Charger enable input. This active low input, if set high, suspends charge and places the device in the low-power sleep mode. Do not pull up this input to VTSB. |
CELLS | 13 | 13 | I | Available on parts with fixed output voltage. Ground or float for single-cell operation (4.2 V). For two-cell operation (8.4 V) pull up this pin with a resistor to VCC. | |||
CMODE | 7 | 7 | I | Charge mode selection: low for precharge as set by ISET2 pin and high (pull up to VTSB or <7 V) for fast charge as set by ISET1. | |||
FB | 13 | 13 | I | Output voltage analog feedback adjustment. Connect the output of a resistive voltage divider powered from the battery terminals to this node to adjust the output battery voltage regulation. | |||
IN | 3, 4 | 3, 4 | 3, 4 | 3, 4 | 3, 4 | I | Charger input voltage. |
ISET1 | 8 | 8 | 8 | 8 | 8 | I/O | Charger current set point 1 (fast charge). Use a resistor to ground to set this value. |
ISET2 | 9 | 9 | 9 | 9 | 9 | I/O | Charge current set point 2 (precharge and termination), set by a resistor connected to ground. A low-level CMODE signal selects the ISET2 charge rate, but if the battery voltage reaches the regulation set point, bqSWITCHER™ changes to voltage regulation regardless of CMODE input. |
N/C | 13 | 19 | 19 | - | No connection. This pin must be left floating in the application. | ||
OUT | 1 | 1 | 1 | 1 | 1 | O | Charge current output inductor connection. Connect a zener TVS diode between OUT pin and PGND pin to clamp the voltage spike to protect the power MOSFETs during abnormal conditions. |
20 | 20 | 20 | 20 | 20 | O | ||
PG | 5 | 5 | 5 | 5 | 5 | O | Power-good status output (open drain). The transistor turns on when a valid VCC is detected. It is turned off in the sleep mode. PG can be used to drive a LED or communicate with a host processor. |
PGND | 17,18 | 17,18 | 17,18 | 17,18 | 17, 18 | Power ground input | |
SNS | 15 | 15 | 15 | 15 | 15 | I | Charge current-sense input. Battery current is sensed via the voltage drop developed on this pin by an external sense resistor in series with the battery pack. A 0.1-μF capacitor to PGND is required. |
STAT1 | 2 | 2 | 2 | 2 | 2 | O | Charge status 1 (open-drain output). When the transistor turns on indicates charge in process. When it is off and with the condition of STAT2 indicates various charger conditions (See Table 1) |
STAT2 | 19 | 19 | 19 | O | Charge status 2 (open-drain output). When the transistor turns on indicates charge is done. When it is off and with the condition of STAT1 indicates various charger conditions (See Table 1) | ||
TS | 12 | 12 | 12 | 12 | 12 | I | Temperature sense input. This input monitors its voltage against an internal threshold to determine if charging is allowed. Use an NTC thermistor and a voltage divider powered from VTSB to develop this voltage. (See Figure 4) |
TTC | 7 | 7 | 7 | I | Timer and termination control. Connect a capacitor from this node to GND to set the bqSWITCHER™ timer. When this input is low, the timer and termination detection are disabled. | ||
VCC | 6 | 6 | 6 | 6 | 6 | I | Analog device input. A 0.1 μF capacitor to VSS is required. |
VSS | 10 | 10 | 10 | 10 | 10 | Analog ground input | |
VTSB | 11 | 11 | 11 | 11 | 11 | O | TS internal bias regulator voltage. Connect capacitor (with a value between a 0.1-μF and 1-μF) between this output and VSS. |
Exposed Thermal Pad |
Pad | Pad | Pad | Pad | Pad | There is an internal electrical connection between the exposed thermal pad and VSS. The exposed thermal pad must be connected to the same potential as the VSS pin on the printed circuit board. The power pad can be used as a star ground connection between VSS and PGND. A common ground plane may be used. VSS pin must be connected to ground at all times. |
MIN | MAX | UNIT | ||
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Supply voltage (with respect to VSS) | IN, VCC | 20 | V | |
Input voltage (with respect to VSS and PGND) | STAT1, STAT2, PG, CE, CELLS, SNS, BAT | –0.3 | 20 | V |
OUT | –0.7 | 20 | V | |
CMODE, TS, TTC | 7 | V | ||
VTSB | 3.6 | V | ||
ISET1, ISET2 | 3.3 | V | ||
Voltage difference between SNS and BAT inputs (VSNS – VBAT) | ±1 | V | ||
Output sink | STAT1, STAT2, PG | 10 | mA | |
Output current (average) | OUT | 2.2 | A | |
Operating free-air temperature, TA | –40 | 85 | °C | |
Junction temperature, TJ | –40 | 125 | °C | |
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds | 300 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) | ±500 |
MIN | NOM | MAX | UNIT | |
---|---|---|---|---|
Supply voltage, VCC and IN (Tie together) | 4.35 (1) | 16 (2) | V | |
Operating junction temperature range, TJ | –40 | 125 | °C |
THERMAL METRIC (1) | bq241xx | UNIT | |
---|---|---|---|
RHL (VQFN) | |||
20 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 39.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 39.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 15.8 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.6 | °C/W |
ψJB | Junction-to-board characterization parameter | 15.8 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 3.6 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT CURRENTS | ||||||
I(VCC) | VCC supply current | VCC > VCC(min), PWM switching | 10 | mA | ||
VCC > VCC(min), PWM NOT switching | 5 | |||||
VCC > VCC(min), CE = HIGH | 315 | μA | ||||
I(SLP) | Battery discharge sleep current, (SNS, BAT, OUT, FB pins) | 0°C ≤ TJ ≤ 65°C, VI(BAT) = 4.2 V, VCC < V(SLP) or VCC > V(SLP) but not in charge |
3.5 | μA | ||
0°C ≤ TJ ≤ 65°C, VI(BAT) = 8.4 V, VCC < V(SLP) or VCC > V(SLP) but not in charge |
5.5 | |||||
0°C ≤ TJ ≤ 65°C, VI(BAT) = 12.6 V, VCC < V(SLP) or VCC > V(SLP) but not in charge |
7.7 | |||||
VOLTAGE REGULATION | ||||||
VOREG | Output voltage, bq24103/03A/04/13/13A | CELLS = Low, in voltage regulation | 4.2 | V | ||
CELLS = High, in voltage regulation | 8.4 | |||||
Output voltage, bq24100/08/09 | Operating in voltage regulation | 4.2 | ||||
VIBAT | Feedback regulation REF for bq24105/15 only (W/FB) | IIBAT = 25 nA typical into pin | 2.1 | V | ||
Voltage regulation accuracy | TA = 25°C | –0.5% | 0.5% | |||
–1% | 1% | |||||
CURRENT REGULATION - FAST CHARGE | ||||||
IOCHARGE | Output current range of converter | VLOWV ≤ VI(BAT) < VOREG, V(VCC) - VI(BAT) > V(DO-MAX) |
150 | 2000 | mA | |
VIREG | Voltage regulated across R(SNS) Accuracy | 100 mV ≤ VIREG≤ 200 mV, | –10% | 10% | ||
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Programmed Where 5 kΩ ≤ RSET1 ≤ 10 kΩ, Select RSET1 to program VIREG, VIREG(measured) = IOCHARGE + RSNS (–10% to 10% excludes errors due to RSET1 and R(SNS) tolerances) |
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V(ISET1) | Output current set voltage | V(LOWV) ≤ VI(BAT) ≤ VO(REG), V(VCC) ≤ VI(BAT) × V(DO-MAX) |
1 | V | ||
K(ISET1) | Output current set factor | VLOWV ≤ VI(BAT) < VO(REG) , V(VCC) ≤ VI(BAT) + V(DO-MAX) |
1000 | V/A | ||
PRECHARGE AND SHORT-CIRCUIT CURRENT REGULATION | ||||||
VLOWV | Precharge to fast-charge transition voltage threshold, BAT, bq24100/03/03A/04/05/08/09 ICs only |
68 | 71.4 | 75 | %VO(REG) | |
t | Deglitch time for precharge to fast charge transition, | Rising voltage; tRISE, tFALL = 100 ns, 2-mV overdrive |
20 | 30 | 40 | ms |
IOPRECHG | Precharge range | VI(BAT) < VLOWV, t < tPRECHG | 15 | 200 | mA | |
V(ISET2) | Precharge set voltage, ISET2 | VI(BAT) < VLOWV, t < tPRECHG | 100 | mV | ||
K(ISET2) | Precharge current set factor | 1000 | V/A | |||
VIREG-PRE | Voltage regulated across RSNS-Accuracy | 100 mV ≤ VIREG-PRE ≤ 100 mV, | –20% | 20% | ||
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(PGM) Where 1.2 kΩ ≤ RSET2 ≤ 10 kΩ, Select RSET1 to program VIREG-PRE, VIREG-PRE (Measured) = IOPRE-CHG × RSNS (–20% to 20% excludes errors due to RSET1 and RSNS tolerances) |
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CHARGE TERMINATION (CURRENT TAPER) DETECTION | ||||||
ITERM | Charge current termination detection range | VI(BAT) > VRCH | 15 | 200 | mA | |
VTERM | Charge termination detection set voltage, ISET2 | VI(BAT) > VRCH | 100 | mV | ||
K(ISET2) | Termination current set factor | 1000 | V/A | |||
Charger termination accuracy | VI(BAT) > VRCH | –20% | 20% | |||
tdg-TERM | Deglitch time for charge termination | Both rising and falling, 2-mV overdrive tRISE, tFALL = 100 ns |
20 | 30 | 40 | ms |
TEMPERATURE COMPARATOR AND VTSB BIAS REGULATOR | ||||||
%LTF | Cold temperature threshold, TS, % of bias | VLTF = VO(VTSB) × % LTF/100 | 72.8% | 73.5% | 74.2% | |
%HTF | Hot temperature threshold, TS, % of bias | VHTF = VO(VTSB) × % HTF/100 | 33.7% | 34.4% | 35.1% | |
%TCO | Cutoff temperature threshold, TS, % of bias | VTCO = VO(VTSB) × % TCO/100 | 28.7% | 29.3% | 29.9% | |
LTF hysteresis | 0.5% | 1% | 1.5% | |||
tdg-TS | Deglitch time for temperature fault, TS | Both rising and falling, 2-mV overdrive tRISE, tFALL = 100 ns |
20 | 30 | 40 | ms |
Deglitch time for temperature fault, TS, bq24109, bq24104 | 500 | |||||
VO(VTSB) | TS bias output voltage | VCC > VIN(min), I(VTSB) = 10 mA 0.1 μF ≤ CO(VTSB) ≤ 1 μF |
3.15 | V | ||
VO(VTSB) | TS bias voltage regulation accuracy | VCC > IN(min), I(VTSB) = 10 mA 0.1 μF ≤ CO(VTSB) ≤ 1 μF |
–10% | 10% | ||
BATTERY RECHARGE THRESHOLD | ||||||
VRCH | Recharge threshold voltage | Below VOREG | 75 | 100 | 125 | mV/cell |
tdg-RCH | Deglitch time | VI(BAT) < decreasing below threshold, tFALL = 100 ns 10-mV overdrive |
20 | 30 | 40 | ms |
STAT1, STAT2, AND PG OUTPUTS | ||||||
VOL(STATx) | Low-level output saturation voltage, STATx | IO = 5 mA | 0.5 | V | ||
VOL(PG) | Low-level output saturation voltage, PG | IO = 10 mA | 0.1 | |||
CE CMODE, CELLS INPUTS | ||||||
VIL | Low-level input voltage | IIL = 5 μA | 0 | 0.4 | V | |
VIH | High-level input voltage | IIH = 20 μA | 1.3 | VCC | ||
TTC INPUT | ||||||
tPRECHG | Precharge timer | 1440 | 1800 | 2160 | s | |
tCHARGE | Programmable charge timer range | t(CHG) = C(TTC) × K(TTC) | 25 | 572 | minutes | |
Charge timer accuracy | 0.01 μF ≤ C(TTC) ≤ 0.18 μF | -10% | 10% | |||
KTTC | Timer multiplier | 2.6 | min/nF | |||
CTTC | Charge time capacitor range | 0.01 | 0.22 | μF | ||
VTTC_EN | TTC enable threshold voltage | V(TTC) rising | 200 | mV | ||
SLEEP COMPARATOR | ||||||
VSLP-ENT | Sleep-mode entry threshold | 2.3 V ≤ VI(OUT) ≤ VOREG, for 1 or 2 cells | VCC ≤ VIBAT +5 mV | VCC ≤ VIBAT +75 mV | V | |
VI(OUT) = 12.6 V, RIN = 1 kΩ bq24105/15 (1) |
VCC ≤ VIBAT -4 mV | VCC ≤ VIBAT +73 mV | ||||
VSLP-EXIT | Sleep-mode exit hysteresis, | 2.3 V ≤ VI(OUT)≤ VOREG | 40 | 160 | mV | |
tdg-SLP | Deglitch time for sleep mode | VCC decreasing below threshold, tFALL = 100 ns, 10-mV overdrive, PMOS turns off |
5 | μs | ||
VCC decreasing below threshold, tFALL = 100 ns, 10-mV overdrive, STATx pins turn off |
20 | 30 | 40 | ms | ||
UVLO | ||||||
VUVLO-ON | IC active threshold voltage | VCC rising | 3.15 | 3.30 | 3.50 | V |
IC active hysteresis | VCC falling | 120 | 150 | mV | ||
PWM | ||||||
Internal P-channel MOSFET on-resistance | 7 V ≤ VCC ≤ VCC(max) | 400 | mΩ | |||
4.5 V ≤ VCC ≤ 7 V | 500 | |||||
Internal N-channel MOSFET on-resistance | 7 V ≤ VCC ≤ VCC(max) | 130 | ||||
4.5 V ≤ VCC ≤ 7 V | 150 | |||||
fOSC | Oscillator frequency | 1.1 | MHz | |||
Frequency accuracy | –9% | 9% | ||||
DMAX | Maximum duty cycle | 100% | ||||
DMIN | Minimum duty cycle | 0% | ||||
tTOD | Switching delay time (turn on) | 20 | ns | |||
tsyncmin | Minimum synchronous FET on time | 60 | ns | |||
Synchronous FET minimum current-off threshold (2) | 50 | 400 | mA | |||
BATTERY DETECTION | ||||||
IDETECT | Battery detection current during time-out fault | VI(BAT) < VOREG – VRCH | 2 | mA | ||
IDISCHRG1 | Discharge current | VSHORT < VI(BAT) < VOREG – VRCH | 400 | μA | ||
tDISCHRG1 | Discharge time | VSHORT < VI(BAT) < VOREG – VRCH | 1 | s | ||
IWAKE | Wake current | VSHORT < VI(BAT) < VOREG – VRCH | 2 | mA | ||
tWAKE | Wake time | VSHORT < VI(BAT) < VOREG – VRCH | 0.5 | s | ||
IDISCHRG2 | Termination discharge current | Begins after termination detected, VI(BAT) ≤ VOREG |
400 | μA | ||
tDISCHRG2 | Termination time | 262 | ms | |||
OUTPUT CAPACITOR | ||||||
COUT | Required output ceramic capacitor range from SNS to PGND, between inductor and RSNS | 4.7 | 10 | 47 | μF | |
CSNS | Required SNS capacitor (ceramic) at SNS pin | 0.1 | μF | |||
PROTECTION | ||||||
VOVP | OVP threshold voltage | Threshold over VOREG to turn off P-channel MOSFET, STAT1, and STAT2 during charge or termination states | 110 | 117 | 121 | %VO(REG) |
ILIMIT | Cycle-by-cycle current limit | 2.6 | 3.6 | 4.5 | A | |
VSHORT | Short-circuit voltage threshold, BAT | VI(BAT) falling | 1.95 | 2 | 2.05 | V/cell |
ISHORT | Short-circuit current | VI(BAT) ≤ VSHORT | 35 | 65 | mA | |
TSHTDWN | Thermal trip | 165 | °C | |||
Thermal hysteresis | 10 | °C |
PACKAGE | θJA | θJC | TA < 40°C POWER RATING |
DERATING FACTOR ABOVE TA = 40°C |
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RHL (1) | 46.87°C/W | 2.5°C/W | 1.81 W | 0.021 W/°C |