SLUSB80E September   2012  – January 2018

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Comparisons
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Operational Flow Chart
    4. 9.4 Feature Description
      1. 9.4.1 Input Voltage Protection
        1. 9.4.1.1 Input Overvoltage Protection
        2. 9.4.1.2 Bad Adaptor Detection/Rejection
        3. 9.4.1.3 Sleep Mode
        4. 9.4.1.4 Input Voltage Based DPM (Special Charger Voltage Threshold)
      2. 9.4.2 Battery Protection
        1. 9.4.2.1 Output Overvoltage Protection
        2. 9.4.2.2 Battery Detection at Power Up in DEFAULT Mode
        3. 9.4.2.3 Battery Short Protection
        4. 9.4.2.4 Battery Detection in Host Mode
      3. 9.4.3 DEFAULT Mode
      4. 9.4.4 USB Friendly Power Up
      5. 9.4.5 Input Current Limiting At Power Up
    5. 9.5 Device Functional Modes
      1. 9.5.1 Charge Mode Operation
        1. 9.5.1.1 Charge Profile
      2. 9.5.2 PWM Controller in Charge Mode
      3. 9.5.3 Battery Charging Process
      4. 9.5.4 Thermal Regulation and Protection
      5. 9.5.5 Charge Status Output, STAT Pin
      6. 9.5.6 Control Bits in Charge Mode
        1. 9.5.6.1 CE Bit (Charge Mode)
        2. 9.5.6.2 RESET Bit
        3. 9.5.6.3 OPA_Mode Bit
      7. 9.5.7 Control Pins in Charge Mode
        1. 9.5.7.1 CD Pin (Charge Disable)
      8. 9.5.8 BOOST Mode Operation
        1. 9.5.8.1 PWM Controller in Boost Mode
        2. 9.5.8.2 Boost Start Up
        3. 9.5.8.3 PFM Mode at Light Load
        4. 9.5.8.4 Protection in Boost Mode
          1. 9.5.8.4.1 Output Overvoltage Protection
          2. 9.5.8.4.2 Output Overload Protection
          3. 9.5.8.4.3 Battery Overvoltage Protection
        5. 9.5.8.5 STAT Pin in Boost Mode
      9. 9.5.9 High Impedance (Hi-Z) Mode
    6. 9.6 Programming
      1. 9.6.1 Serial Interface Description
        1. 9.6.1.1 F/S Mode Protocol
        2. 9.6.1.2 H/S Mode Protocol
        3. 9.6.1.3 I2C Update Sequence
        4. 9.6.1.4 Slave Address Byte
        5. 9.6.1.5 Register Address Byte
    7. 9.7 Register Description
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Typical Application
        1. 10.1.1.1 Design Requirements
        2. 10.1.1.2 Detailed Design Procedure
      2. 10.1.2 Charge Current Sensing Resistor Selection Guidelines
      3. 10.1.3 Output Inductor and Capacitance Selection Guidelines
    2. 10.2 Typical Performance Curves
  11. 11Power Supply Recommendations
    1. 11.1 System Load After Sensing Resistor
      1. 11.1.1 The Advantages:
      2. 11.1.2 Design Requirements and Potential Issues:
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Package Summary
      1. 14.1.1 Chip Scale Packaging Dimensions

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

The bq24157 is a compact, flexible, high-efficiency, USB-friendly, switch-mode charge management solution for single-cell Li-ion and Li-polymer batteries used in a wide range of portable applications. The bq24157 integrates a synchronous PWM controller, power MOSFETs, input current sensing, high-accuracy current and voltage regulation, and charge termination, into a small DSBGA package. The charge parameters can be programmed through an I2C interface.

10.1.1 Typical Application

VBUS = 5 V, ICHARGE = 1250 mA, VBAT = 3.5 to 4.44 V (adjustable).

bq24157 app2_cir_lusb80.gif Figure 23. I2C Controlled 1-Cell USB Charger Application Circuit with USB OTG Support.

10.1.1.1 Design Requirements

Use the following typical application design procedure to select external components values for the bq24157 device.

Specification Test Condition MIN TYP MAX UNIT
Input DC voltage, VIN Input voltage from AC adapter input 4 5 6 V
Input current Maximum input current from AC adapter input 0.1 0.1 to 0.5 1.5 A
Charge current Battery charge current 0.325 0.7 1.55 A
Output regulation voltage Voltage applied at VBAT 0 3 to 4.2 4.44 V
Operating junction temperature range, TJ 0 125 °C

10.1.1.2 Detailed Design Procedure

Systems Design Specifications:

  • VBUS = 5 V
  • VBAT = 4.2 V (1-Cell)
  • I(charge) = 1.25 A
  • Inductor ripple current = 30% of fast charge current
  1. Determine the inductor value (LOUT) for the specified charge current ripple:

    2. bq24157 q_lo_vbat_lus824.gif , the worst case is when battery voltage is as close as to half of the input voltage.

    Equation 1. bq24157 q_lo_25_lus824.gif

    LOUT = 1.11 μH

    Select the output inductor to standard 1 μH. Calculate the total ripple current with using the 1-μH inductor:

    Equation 2. bq24157 q_dlo_vbat_lus824.gif
    Equation 3. bq24157 q_dlo_25_lus824.gif

    ΔIL = 0.42 A

    Calculate the maximum output current:

    Equation 4. bq24157 q_lpk_io_lus824.gif
    Equation 5. bq24157 q_lpk_125_lus824.gif

    ILPK = 1.46 A

    Select 2.5mm by 2mm 1-μH 1.5-A surface mount multi-layer inductor. The suggested inductor part numbers are shown as following.

    Table 10. Inductor Part Numbers(1)

    PART NUMBER INDUCTANCE SIZE MANUFACTURER
    LQM2HPN1R0MJ0 1 μH 2.5 x 2.0 mm Murata
    MIPS2520D1R0 1 μH 2.5 x 2.0 mm FDK
    MDT2520-CN1R0M 1 μH 2.5 x 2.0 mm TOKO
    CP1008 1 μH 2.5 x 2.0 mm Inter-Technical

    spacer

  2. Determine the output capacitor value (COUT) using 40 kHz as the resonant frequency:
    3. Equation 6. bq24157 q_fo_lus824.gif
    Equation 7. bq24157 q_cout_1_lus824.gif
    Equation 8. bq24157 q_cout_2_lus824.gif

    COUT = 15.8 μF

    Select two 0603 X5R 6.3V 10-μF ceramic capacitors in parallel i.e., Murata GRM188R60J106M.

  3. Determine the sense resistor using the following equation:
    4. Equation 9. bq24157 q_rsns_vsns_lus824.gif

    The maximum sense voltage across the sense resistor is 85 mV. In order to get a better current regulation accuracy, V(RSNS) should equal 85mV, and calculate the value for the sense resistor.

    Equation 10. bq24157 q_rsns_85_lus824.gif

    R(SNS) = 68 mΩ

    This is a standard value. If it is not a standard value, then choose the next close value and calculate the real charge current. Calculate the power dissipation on the sense resistor:

    P(RSNS) = I(CHARGE) 2 × R(SNS)

    P(RSNS) = 1.252 × 0.068

    P(RSNS) = 0.106 W

    Select 0402 0.125-W 68-mΩ 2% sense resistor, i.e. Panasonic ERJ2BWGR068.

  4. Measured efficiency and total power loss with different inductors are shown in Figure 24. SW node and inductor current waveform are shown in Figure 34.
bq24157 pwr_loss_lus824.gif Figure 24. Measured Efficiency and Power Loss

10.1.2 Charge Current Sensing Resistor Selection Guidelines

Both the termination current range and charge current range depend on the sensing resistor (RSNS). The termination current step (IOTERM_STEP) can be calculated using Equation 11:

Equation 11. bq24157 q_ioterm_lus824.gif

Table 11 shows the termination current settings for three sensing resistors.

Table 11. Termination Current Settings for 55-mΩ, 68-mΩ, 100-mΩ Sense Resistors

BIT VI(TERM) (mV) I(TERM) (mA)
R(SNS) = 55mΩ		 I(TERM) (mA)
R(SNS) = 68mΩ		 I(TERM) (mA)
R(SNS) = 100mΩ
VI(TERM2) 13.6 247 200 136
VI(TERM1) 6.8 124 100 68
VI(TERM0) 3.4 62 50 34
Offset 3.4 62 50 34

For example, with a 68-mΩ sense resistor, V(ITERM2) = 1, V(ITERM1) = 0, and V(ITERM0) = 1, ITERM = [ (13.6 mV x 1) + (6.8 mV x 0) + (3.4 mV x 1) + 3.4 mV ] / 68 mΩ = 200 mA + 0 + 50 mA + 50 mA = 300 mA.

The charge current step (IO(CHARGE_STEP)) is calculated using Equation 12:

Equation 12. bq24157 q_iochg_lus824.gif

Table 12 shows the charge current settings for three sensing resistors.

Table 12. Charge Current Settings for 55-mΩ, 68-mΩ and 100-mΩ Sense Resistors

BIT VI(REG) (mV) IO(CHARGE) (mA)
R(SNS) = 55mΩ		 IO(CHARGE) (mA)
R(SNS) = 68mΩ 		IO(CHARGE) (mA)
R(SNS) = 100mΩ
VI(CHRG3) 27.2 495 400 272
VI(CHRG2) 13.6 247 200 136
VI(CHRG1) 6.8 124 100 68
VI(CHRG0) N/A N/A N/A N/A
Offset 37.4 680 550 374

For example, with a 68-mΩ sense resistor, V(CHRG3) = 1, V(CHRG2) = 1, V(ICHRG1) = 1, ICHRG = [ (27.2 mV x 1) + (13.6 mV x 1) + (6.8 mV x 1) + 37.4 mV ] / 68 mΩ = 400 mA + 200 + 100 + 550 mA = 1250 mA.

10.1.3 Output Inductor and Capacitance Selection Guidelines

The IC provides internal loop compensation. With the internal loop compensation, the highest stability occurs when the LC resonant frequency, fo, is approximately 40 kHz (20 kHz to 80 kHz). Equation 13 can be used to calculate the value of the output inductor, LOUT, and output capacitor, COUT.

Equation 13. bq24157 q_fo_lus824.gif

To reduce the output voltage ripple, a ceramic capacitor with the capacitance between 4.7 μF and 47 μF is recommended for COUT, see the application section for components selection.

VBUS = 5 V, ICHARGE = 1250 mA, VBAT = 3.5 V to 4.44 V (Adjustable).

10.2 Typical Performance Curves

Using circuit shown in Figure 23, TA = 25°C, unless otherwise specified.

bq24157 adp1_ins_lusa27.gif
VBUS = 0-5V, Iin_limit = 500mA, Voreg = 4.2V
VBAT = 3.5V, ICHG = 550mA, 32S mode
Figure 25. Adapter Insertion
bq24157 pwrup_153_lusa27.gif
VBUS = 5 V No Battery Connected
Figure 27. Battery Detection at Power Up
bq24157 boost1_pfm_lusa27.gif
VBUS = 5.05 V, VBAT = 3.5V, IBUS = 42 mA
Figure 29. BOOST Waveform (PFM Mode)
bq24157 stp1_up_res_lusa27.gif
VBUS = 5.05 V, VBAT = 3.5V, IBUS = 0-217 mA
Figure 31. Load Step Up Response (BOOST Mode)
bq24157 bat1_ins_rm_lusa27.gif
VBUS = 5 V VBAT = 3.4 V Iin_limit = 500 mA
Figure 26. Battery Insertion/Removal (HOST Mode)
bq24157 boost1_pwm_lusa27.gif
VBUS = 5.05 V, VBAT = 3.5V, IBUS = 217 mA
Figure 28. BOOST Waveform (PWM Mode)
bq24157 load_stepup-resp_boost_lusax5.gif
VBUS = 5.05, VBAT = 3.5V, IBUS = 0-360 mA
Figure 30. Load Step Up Response (BOOST Mode)
bq24157 load_stepdown-resp_boost_lusax5.gif
VBUS = 5.05, VBAT = 3.5V, IBUS = 360-0 mA
Figure 32. Load Step Down Response (BOOST Mode)