9.3.1 Battery Voltage Regulation

The bq24171 offers a high-accuracy voltage regulator on for the charging voltage.

The bq24171 uses external resistor divider for voltage feedback and regulate to internal 2.1-V voltage reference on FB pin. Use the following equation for the regulation voltage for bq24171:

Equation 1.

where

• R2 is connected from FB to the battery.
• R1 is connected from FB to GND.

9.3.2 Battery Current Regulation

The ISET input sets the maximum charging current. Battery current is sensed by current-sensing resistor RSR connected between SRP and SRN. The full-scale differential voltage between SRP and SRN is 40 mV maximum. The equation for charge current is:

Equation 2.

The valid input voltage range of ISET is up to 0.8 V. With 10-mΩ sense resistor, the maximum output current is
4 A. With 20-mΩ sense resistor, the maximum output current is 2 A.

The charger is disabled when ISET pin voltage is below 40 mV and is enabled when the ISET pin voltage is above 120 mV. For 10-mΩ current-sensing resistor, the minimum fast charge current must be higher than 600 mA.

Under high ambient temperature, the charge current will fold back to keep IC temperature not exceeding 120°C.

9.3.3 Battery Precharge Current Regulation

On power up, if the battery voltage is below the V_LOWV threshold, the bq24171 applies the precharge current to the battery. This precharge feature is intended to revive deeply discharged cells. If the V_LOWV threshold is not reached within 30 minutes of initiating precharge, the charger turns off and a FAULT is indicated on the status pins.

For bq24171, the precharge current is set as 10% of the fast charge rate set by ISET voltage.

Equation 3.

9.3.4 Input Current Regulation

The total input current from an AC adapter or other DC sources is a function of the system supply current and the battery charging current. System current normally fluctuated as portions of the systems are powered up or down. Without Dynamic Power Management (DPM), the source must be able to supply the maximum system current and the maximum available charger input current simultaneously. By using DPM, the input current regulator reduces the charging current when the summation of system power and charge power exceeds the maximum input power. Therefore, the current capability of the AC adapter can be lowered, reducing system cost.

Input current is set by the voltage on ACSET pin using the following equation:

Equation 4.

The ACP and ACN pins are used to sense across RAC with default value of 10 mΩ. However, resistors of other values can also be used. A larger sense resistor will give a larger sense voltage and higher regulation accuracy, at the expense of higher conduction loss.

9.3.5 Charge Termination, Recharge, and Safety Timers

The charger monitors the charging current during the voltage regulation phase. Termination is detected when the FB voltage is higher than recharge threshold and the charge current is less than the termination current threshold, as calculated below:

Equation 5.

where

• V_ISET is the voltage on the ISET pin.
• R_SR is the sense resistor.

There is a 25-ms deglitch time during transition between fast charge and precharge.

As a safety backup, the charger also provides an internal fixed 30-minute precharge safety timer and a programmable fast charge timer. The fast charge time is programmed by the capacitor connected between the TTC pin and AGND, and is given by the formula:

Equation 6.

where

• C_TTC is the capacitor connected to TTC.
• K_TTC is the constant multiplier.

A new charge cycle is initiated when one of the following conditions occurs:

• The battery voltage falls below the recharge threshold
• A power-on-reset (POR) event occurs
• ISET pin toggled below 40 mV (disable charge) and above 120 mV (enable charge)

Pull the TTC pin to AGND to disable both termination and fast charge safety timer (reset timer). Pull the TTC pin to VREF to disable the safety timer, but allow charge termination.

9.3.6 Power Up

The charge uses a SLEEP comparator to determine the source of power on the AVCC pin because AVCC can be supplied either from the battery or the adapter. With the adapter source present, if the AVCC voltage is greater than the SRN voltage, the charger exits SLEEP mode. If all conditions are met for charging, the charger then starts charge the battery (see Enable and Disable Charging). If SRN voltage is greater than AVCC, the charger enters low quiescent current SLEEP mode to minimize current drain from the battery. During SLEEP mode, the VREF output turns off and the STAT pin goes to high impedance.

If AVCC is below the UVLO threshold, the device is disabled.

9.3.7 Input Undervoltage Lockout (UVLO)

The system must have a minimum AVCC voltage to allow proper operation. This AVCC voltage could come from either input adapter or battery because a conduction path exists from the battery to AVCC through the high-side NMOS body diode. When AVCC is below the UVLO threshold, all circuits on the IC are disabled.

9.3.8 Input Overvoltage/Undervoltage Protection

ACOV provides protection to prevent system damage due to high input voltage. In bq24171, once the voltage on OVPSET is above the 1.6-V ACOV threshold or below the 0.5-V ACUV threshold, charge is disabled and input MOSFETs turn off. The bq24171 provides flexibility to set the input qualification threshold.

9.3.9 Enable and Disable Charging

The following conditions have to be valid before charging is enabled:

• ISET pin above 120 mV.
• Device is not in UVLO mode (that is, V_AVCC > V_UVLO).
• Device is not in SLEEP mode (that is, V_AVCC > V_SRN).
• OVPSET voltage is from 0.5 V to 1.6 V to qualify the adapter.
• 1.5-s delay is complete after initial power up.
• REGN LDO and VREF LDO voltages are at correct levels.
• Thermal Shutdown (TSHUT) is not valid.
• TS fault is not detected.
• ACFET turns on (see System Power Selector for details).

One of the following conditions stops ongoing charging:

• ISET pin voltage is below 40 mV.
• Device is in UVLO mode.
• Adapter is removed, causing the device to enter SLEEP mode.
• OVPSET voltage indicates the adapter is not valid.
• REGN or VREF LDO voltage is overloaded.
• TSHUT temperature threshold is reached.
• TS voltage goes out of range, indicating the battery temperature is too hot or too cold.
• ACFET turns off.
• TTC timer expires or precharge timer expires.

9.3.10 System Power Selector

The IC automatically switches adapter or battery power to the system load. The battery is connected to the system by default during power up or during SLEEP mode. When the adapter plugs in and the voltage is above the battery voltage, the IC exits SLEEP mode. The battery is disconnected from the system and the adapter is connected to the system after exiting SLEEP. An automatic break-before-make logic prevents shoot-through currents when the selectors switch.

The ACDRV is used to drive a pair of back-to-back N-channel power MOSFETs between adapter and ACP with sources connected together to CMSRC. The N-channel FET with the drain connected to the ACP (Q2, RBFET) provides reverse battery discharge protection, and minimizes system power dissipation with its low-RDS_ON. The other N-channel FET with drain connected to adapter input (Q1, ACFET) separates battery from adapter, and provides a limited dI/dt when connecting the adapter to the system by controlling the FET turnon time. The /BATDRV controls a P-channel power MOSFET (Q3, BATFET) placed between battery and system with drain connected to battery.

Before the adapter is detected, the ACDRV is pulled to CMSRC to keep ACFET off, disconnecting the adapter from system. /BATDRV stays at ACN - 6 V (clamp to ground) to connect battery to system if all the following conditions are valid:

• V_AVCC > V_UVLO (battery supplies AVCC)
• V_ACN < V_SRN + 200 mV

After the device comes out of SLEEP mode, the system begins to switch from battery to adapter. The AVCC voltage has to be 300 mV above SRN to enable the transition. The break-before-make logic keeps both ACFET and BATFET off for 10 µs before ACFET turns on. This prevents shoot-through current or any large discharging current from going into the battery. The /BATDRV is pulled up to ACN and the ACDRV pin is set to CMSRC +
6 V by an internal charge pump to turn on N-channel ACFET, connecting the adapter to the system if all the following conditions are valid:

• V_ACUV < V_OVPSET < V_ACOV
• V_AVCC > V_SRN + 300 mV

When the adapter is removed, the IC turns off ACFET and enters SLEEP mode.

BATFET keeps off until the system drops close to SRN. The BATDRV pin is driven to ACN - 6 V by an internal regulator to turn on P-channel BATFET, connecting the battery to the system.

Asymmetrical gate drive provides fast turnoff and slow turnon of the ACFET and BATFET to help the break-before-make logic and to allow a soft-start at turnon of both MOSFETs. The delay time can be further increased by putting a capacitor from gate to source of the power MOSFETs.

9.3.11 Converter Operation

The bq24171 employs a 1.6-MHz constant-frequency step-down switching regulator. The fixed-frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible noise region.

A type III compensation network allows using ceramic capacitors at the output of the converter. An internal saw-tooth ramp is compared to the internal error control signal to vary the duty cycle of the converter. The ramp height is proportional to the AVCC voltage to cancel out any loop gain variation due to a change in input voltage, and simplifies the loop compensation. Internal gate drive logic allows achieving 97% duty cycle before pulse skipping starts.

9.3.12 Automatic Internal Soft-Start Charger Current

The charger automatically soft-starts the charger regulation current every time the charger goes into fast charge to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists of stepping-up the charge regulation current into eight evenly divided steps up to the programmed charge current. Each step lasts around 1.6 ms, for a typical rise time of 12.8 ms. No external components are needed for this function.

9.3.13 Charge Overcurrent Protection

The charger monitors top-side MOSFET current by high-side sense FET. When peak current exceeds MOSFET limit, the charger turns off the top-side MOSFET and keeps it off until the next cycle. The charger has a secondary cycle-to-cycle overcurrent protection. The charger monitors the charge current, and prevents the current from exceeding 160% of the programmed charge current. The high-side gate drive turns off when either overcurrent condition is detected, and automatically resumes when the current falls below the overcurrent threshold.

9.3.14 Charge Undercurrent Protection

After the recharge, if the SRP-SRN voltage decreases below 5 mV, then the low-side FET is turned off for the rest of the switching cycle. During discontinuous conduction mode (DCM), the low-side FET turns on for a short period of time when the bootstrap capacitor voltage drops below 4 V to provide refresh charge for the capacitor. This is important to prevent negative inductor current from causing any boost effect in which the input voltage increases as power is transferred from the battery to the input capacitors. This can lead to an overvoltage on the AVCC node and potentially cause damage to the system.

9.3.15 Battery Detection

For applications with removable battery packs, IC provides a battery absent detection scheme to reliably detect insertion or removal of battery packs. The battery detection routine runs on power up, or if battery voltage falls below recharge threshold voltage due to removing a battery or discharging a battery.

Figure 15. Battery Detection Flow Chart

Once the device has powered up, an 8-mA discharge current is applied to the SRN terminal. If the battery voltage falls below the LOWV threshold within 1 second, the discharge source is turned off, and the charger is turned on at low charge current (125 mA). If the battery voltage gets up above the recharge threshold within 500 ms, there is no battery present and the cycle restarts. If either the 500-ms or 1-second timer times out before the respective thresholds are hit, a battery is detected and a charge cycle is initiated.

Figure 16. Battery Detect Timing Diagram

Ensure that the total output capacitance at the battery node is not so large that the discharge current source cannot pull the voltage below the LOWV threshold during the 1-second discharge time. The maximum output capacitances can be calculated according to the following equation:

Equation 7.

where

• C_MAX is the maximum output capacitance.
• I_DISCH is the discharge current.
• t_DISCH is the discharge time.
• R₂ and R₁ are the voltage feedback resistors from the battery to the FB pin.

9.3.15.1 Example

For a 3-cell Li+ charger, with R₂ = 500 kΩ, R₁ = 100 kΩ (giving 12.6 V for voltage regulation), I_DISCH = 8 mA, t_DISCH = 1 second.

Equation 8.

Based on these calculations, no more than 2200 µF should be allowed on the battery node for proper operation of the battery detection circuit.

9.3.16 Battery Short Protection

When SRN pin voltage is lower than 2 V, it is considered as battery short condition during charging period. The charger will shut down immediately for 1 ms, then soft start back to the charging current the same as precharge current. This prevents high current may build in output inductor and cause inductor saturation when battery terminal is shorted during charging. The converter works in nonsynchronous mode during battery short.

9.3.17 Battery Overvoltage Protection

The converter will not allow the high-side FET to turn on until the battery voltage goes below 102% of the regulation voltage. This allows 1-cycle response to an overvoltage condition – such as occurs when the load is removed or the battery is disconnected. A total 6-mA current sink from SRP/SRN to AGND allows discharging the stored output inductor energy that is transferred to the output capacitors. If battery overvoltage condition lasts for more than 30 ms, charge is disabled.

9.3.18 Temperature Qualification and JEITA Guideline

The controller continuously monitors battery temperature by measuring the voltage between the TS pin and GND. A negative temperature coefficient thermistor (NTC) and an external voltage divider typically develop this voltage. The controller compares this voltage against its internal thresholds to determine if charging is allowed. To initiate a charge cycle, the voltage on TS pin must be within the V_T1 to V_T5 thresholds. If V_TS is outside of this range, the controller suspends charge and waits until the battery temperature is within the V_T1 to V_T5 range. During the charge cycle, the battery temperature must be within the V_T1 to V_T5 thresholds. If battery temperature is outside of this range, the controller suspends charge and waits until the battery temperature is within the V_T1 to V_T5 range. The controller suspends charge by turning off the PWM charge FETs. If V_TS is within the range of V_T1 and V_T2, charge voltage regulation on FB pin is 2.1 V and the charge current is reduced to I_CHARGE/2 (To avoid early termination during V_T1 and V_T2 range, fast charge current need to be bigger than 2 times of termination current); if V_TS is within the range of V_T2 and V_T3, the charge voltage regulation on FB pin is 2.1 V; if V_TS is within V_T3 and V_T4, the charge voltage regulation on FB pin is reduced back to 2.05 V; and if V_TS is within V_T4 and V_T5, the charge voltage regulation on FB pin is further reduced to 2.025 V. Figure 17 summarizes the operation. See the Li-ion battery charger solutions for JEITA compliance, SLYT365.

Figure 17. TS Pin, Thermistor Sense Thresholds

Assuming a 103AT NTC thermistor on the battery pack as shown in Figure 18, the values of RT1 and RT2 can be determined by using Equation 9 and Equation 10:

Equation 9.

Equation 10.

Figure 18. TS Resistor Network

For example, 103AT NTC thermistors are used to monitor the battery pack temperature. Select T1 = 0ºC for COLD and T5 = 60ºC for HOT, then we get R_T2 = 6.8 kΩ and R_T1 = 2.2 kΩ as in the design tool. A small RC filter is suggested to use for system-level ESD protection.

9.3.19 MOSFET Short Circuit and Inductor Short Circuit Protection

The IC has a short circuit protection feature. Its cycle-by-cycle current monitoring feature is achieved through monitoring the voltage drop across Rdson of the MOSFETs. The charger will be latched off, but the ACFET keep on to power the system. The only way to reset the charger from latch-off status is remove adapter then plug adapter in again. Meanwhile, STAT is blinking to report the fault condition.

9.3.20 Thermal Regulation and Shutdown Protection

The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the ambient, to keep junctions temperatures low. The internal thermal regulation loop will fold back the charge current to keep the junction temperature from exceeding 120°C. As added level of protection, the charger converter turns off and self-protects whenever the junction temperature exceeds the TSHUT threshold of 150°C. The charger stays off until the junction temperature falls below 130°C.

9.3.21 Timer Fault Recovery

The IC provides a recovery method to deal with timer fault conditions. The following summarizes this method:

Condition 1: The battery voltage is above the recharge threshold and a time-out fault occurs.

Recovery Method: The timer fault will clear when the battery voltage falls below the recharge threshold, and battery detection will begin. A POR or taking ISET below 40 mV will also clear the fault.

Condition 2: The battery voltage is below the recharge threshold and a time-out fault occurs.

Recovery Method: Under this scenario, the IC applies the fault current to the battery. This small current is used to detect a battery removal condition and remains on as long as the battery voltage stays below the recharge threshold. If the battery voltage goes above the recharge threshold, the IC disabled the fault current and executes the recovery method described in Condition 1. A POR or taking ISET below 40 mV will also clear the fault.

9.3.22 Inductor, Capacitor, and Sense Resistor Selection Guidelines

The IC provides internal loop compensation. With this scheme, the best stability occurs when the LC resonant frequency, f_o, is approximately 15 kHz – 25 kHz for the IC.

Equation 11.

Table 2 summarizes typical LC components for various charge currents.

9.3.23 Charge Status Outputs

The open-drain STAT outputs indicate various charger operations as listed in Table 3. These status pins can be used to drive LEDs or communicate with the host processor. OFF indicates that the open-drain transistor is turned off.