11.1 Layout Guidelines

• To obtain optimal performance, the decoupling capacitor from IN to GND (thermal pad) and the output filter capacitors from OUT to GND (thermal pad) must be placed as close as possible to the bq2423xH, with short trace runs to both IN, OUT, and GND (thermal pad).
• All low-current GND connections must be kept separate from the high-current charge or discharge paths from the battery. Use a single-point ground technique incorporating both the small signal ground path and the power ground path.
• The high current charge paths into the IN pin and from the OUT pin must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces.
• The bq2423xH family is packaged in a thermally enhanced MLP package. The package includes a thermal pad to provide an effective thermal contact between the IC and the printed-circuit board (PCB); this thermal pad is also the main ground connection for the device. Connect the thermal pad to the PCB ground connection. Full PCB design guidelines for this package are provided in the application report entitled: QFN/SON PCB Attachment (SLUA271).

11.2 Layout Example

Figure 32. Layout Example

11.3 Thermal Package

The bq2423xH is packaged in a thermally enhanced MLP package. The package includes a thermal pad to provide an effective thermal contact between the IC and the printed-circuit board (PCB). The power pad must be directly connected to the Vss pin. Full PCB design guidelines for this package are provided in the application report entitled: QFN/SON PCB Attachment (SLUA271). The most common measure of package thermal performance is thermal impedance (θ_JA ) measured (or modeled) from the chip junction to the air surrounding the package surface (ambient). The mathematical expression for θ_JA is:

θ_JA = (T_J - T) / P

Where:

T_J = chip junction temperature

T = ambient temperature

P = device power dissipation

Factors that can greatly influence the measurement and calculation of θ_JA include:

• Whether the device is board mounted
• Trace size, composition, thickness, and geometry
• Orientation of the device (horizontal or vertical)
• Volume of the ambient air surrounding the device under test and airflow
• Whether other surfaces are in close proximity to the device being tested

Due to the charge profile of Li-ion batteries, the maximum power dissipation is typically seen at the beginning of the charge cycle when the battery voltage is at its lowest. Typically, after fast charge begins, the pack voltage increases to approximately 3.4 V within the first 2 minutes. The thermal time constant of the assembly typically takes a few minutes to heat up so when doing maximum power dissipation calculations, 3.4 V is a good minimum voltage to use. This is easy to verify, with the system and a fully discharged battery, by plotting temperature on the bottom of the PCB under the IC (pad must have multiple vias), the charge current and the battery voltage as a function of time. The fast-charge current starts to taper off if the part goes into thermal regulation.

The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal PowerFET. It can be calculated from the following equation when a battery pack is being charged :

P = [V_(IN) – V_(OUT)] × I_(OUT) + [V_(OUT) – V_(BAT)] × I_(BAT)

The thermal loop feature reduces the charge current to limit excessive IC junction temperature. It is recommended that the design not run in thermal regulation for typical operating conditions (nominal input voltage and nominal ambient temperatures) and use the feature for nontypical situations such as hot environments or higher than normal input source voltage. With that said, the IC still performs as described, if the thermal loop is always active.