11.1 Layout Guidelines

1. Place the BOOT, PMID, IN, BAT, and LDO capacitors as close as possible to the IC for optimal performance.
2. Connect the inductor as close as possible to the SW pin, and the SYS cap as close as possible to the inductor minimizing noise in the path.
3. Place a 1-μF PMID capacitor as close as possible to the PMID and PGND pins, making the high frequency current loop area as small as possible.
4. The local bypass capacitor from SYS to GND must be connected between the SYS pin and PGND of the IC. This minimizes the current path loop area from the SW pin through the LC filter and back to the PGND pin.
5. Place all decoupling capacitors close to their respective IC pins and as close as possible to PGND (do not place components such that routing interrupts power-stage currents). All small control signals must be routed away from the high-current paths.
6. To reduce noise coupling, use a ground plane if possible, to isolate the noisy traces from spreading its noise all over the board. Put vias inside the PGND pads for the IC.
7. The high-current charge paths into IN, Micro-USB, BAT, SYS, and from the SW pins must be sized appropriately for the maximum charge current to avoid voltage drops in these traces.
8. For high-current applications, the balls for the power paths must be connected to as much copper in the board as possible. This allows better thermal performance because the board conducts heat away from the IC.

11.2 Board Layout

Figure 32. Recommended bq24250C PCB Layout for WCSP Package

11.3 Package Summary

The bq24250C device is available in a 30-bump chip scale package (YFF, NanoFree™). The package dimensions are:

D – 2.427mm ±0.035mm

E – 2.027mm ±0.035mm