bq24292i I2C Controlled 4.5A Single Cell USB/Adapter Charger With Narrow VDC Power Path Management and USB OTG

8.3.1.1 Power-On-Reset (POR)

The internal bias circuits are powered from the higher voltage of VBUS and BAT. When VBUS or VBAT rises above UVLOZ, the sleep comparator, battery depletion comparator and BATFET driver are active. I²C interface is ready for communication and all the registers are reset to default value. The host can access all the registers after POR.

8.3.1.2 Power Up from Battery without DC Source

If only battery is present and the voltage is above depletion threshold (V_{BAT_DEPL}), the BATFET turns on and connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low R_DSON in BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time. The device always monitors the discharge current through BATFET. When the system is overloaded or shorted, the device will immediately turn off BATFET and keep BATFET off until the input source plugs in again.

8.3.1.3 Power Up from DC Source

When the DC source plugs in, the device checks the input source voltage to turn on REGN LDO and all the bias circuits. It also checks the input current limit before starts the buck converter.

8.3.1.4 Converter Power-Up

After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.

The device provides soft-start when ramp up the system rail. When the system rail is below 2.2V, the input current limit is forced to 100mA. After the system rises above 2.2V, the charger device sets the input current limit set by the lower value between register and ILIM pin.

As a battery charger, the device deploys a 1.5MHz step-down switching regulator. The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current and temperature, simplifying output filter design.

A type III compensation network allows using ceramic capacitors at the output of the converter. An internal saw-tooth ramp is compared to the internal error control signal to vary the duty cycle of the converter. The ramp height is proportional to the PMID voltage to cancel out any loop gain variation due to a change in input voltage.

To improve light-load efficiency, the device switches to PFM control at light load when battery is below minimum system voltage setting or charging is disabled. During the PFM operation, the switching duty cycle is set by the ratio of SYS and VBUS.

8.3.1.5 Boost Mode Operation from Battery

The device can operate in boost converter mode to support USB On-The-Go (OTG) standard with fast startup and deliver power from the battery to other portable devices through USB port. The boost mode output current rating meets the USB On-The-Go 500mA output requirement. The maximum output current is 1.3A. The boost operation can be enabled only if all of the following conditions are valid:

• BAT above BATLOWV threshold (V_BATLOWV set by REG04[1])
• VBUS less than BAT+V_SLEEP (in sleep mode)
• Boost mode operation is enabled (OTG pin HIGH and REG01[5:4]=10)
• After t_{OTG_DLY} (22ms typical) delay from boost mode enable

In boost mode, the device employs a 1.5MHz step-up switching regulator. Similar to buck operation, the device switches from PWM operation to PFM operation at light load to improve efficiency.

During boost mode, the status register REG08[7:6] is set to 11, the VBUS output is 5V and the output current can reach up to 500mA or 1.3A, selected via I²C (REG01[0]).

Any fault during boost operation, including VBUS overvoltage or overcurrent, sets the fault register REG09[6] to 1 and an INT is asserted.

8.3.2.1 Narrow VDC Architecture

The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by REG01[3:1]. Even with a fully depleted battery, the system is regulated above the minimum system voltage (default 3.5V).

When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode), and the system is 150mV above the minimum system voltage setting. As the battery voltage rises above the minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the V_DS of BATFET.

When the battery charging is disabled or terminated, the system is always regulated at 150mV above the minimum system voltage setting. The status register REG08[0] goes high when the system is in minimum system voltage regulation.

Figure 10. V(SYS) vs V(BAT)

8.3.2.2 Dynamic Power Management

To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic Power Management (DPM), which continuously monitors the input current and input voltage.

When input source is over-loaded, either the current exceeds the input current limit (REG00[2:0]) or the voltage falls below the input voltage limit (REG00[6:3]). The device then reduces the charge current until the input current falls below the input current limit and the input voltage rises above the input voltage limit.

When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement mode where the BATFET turns on and battery starts discharging so that the system is supported from both the input source and battery.

During DPM mode (either VINDPM or IINDPM), the status register REG08[3] will go high.

Figure 11 shows the DPM response with 9V/1.2A adapter, 3.2V battery, 2.8A charge current and 3.4V minimum system voltage setting.

Figure 11. DPM Response

8.3.2.3 Supplement Mode

When the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is regulated the gate drive of BATFET so that the minimum BATFET V_DS stays at 30mV when the current is low. This prevents oscillation from entering and exiting the supplement mode. As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce R_DSON until the BATFET is in full conduction. At this point onwards, the BATFET V_DS linearly increases with discharge current. Figure 12 shows the V-I curve of the BATFET gate regulation operation. BATFET turns off to exit supplement mode when the battery is below battery depletion threshold.

Figure 12. BATFET V-I Curve

8.3.3.1 Autonomous Charging Cycle

With battery charging enabled at POR (REG01[5:4]=01), the device can complete a charging cycle without host involvement. The device default charging parameters are listed in .

A new charge cycle starts when the following conditions are valid:

• Converter starts
• Battery charging is enabled by I²C register bit (REG01[5:4]) = 01 and CE is low
• No thermistor fault on TS1 and TS2
• No safety timer fault
• BATFET is not forced to turn off (REG07[5])

The charger device automatically terminates the charging cycle when the charging current is below termination threshold and charge voltage is above recharge threshold. When a full battery voltage is discharged below recharge threshold (REG04[0]), the device automatically starts another charging cycle. After charging is done, either toggle CE pin or REG01[5:4] will initiate a new charging cycle.

The STAT output indicates the charging status of charging (LOW), charging complete or charge disable (HIGH) or charging fault (Blinking). The status register REG08[5:4] indicates the different charging phases: 00-charging disable, 01-precharge, 10-fast charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is complete, an INT is asserted to notify the host.

The host can always control the charging operation and optimize the charging parameters by writing to the registers through I²C.

8.3.3.2 Battery Charging Profile

The device charges the battery in three phases: preconditioning, constant current and constant voltage. At the beginning of a charging cycle, the device checks the battery voltage and applies current.

If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will be less than the programmed value. In this case, termination is temporarily disabled and the charging safety timer is counted at half the clock rate.

Figure 13. Battery Charging Profile

8.3.3.3 Battery Path Impedance IR Compensation

To speed up the charging cycle, we would like to stay in constant current mode as long as possible. In real system, the parasitic resistance, including routing, connector, MOSFETs and sense resistor in the battery pack, may force the charger device to move from constant current loop to constant voltage loop too early, extending the charge time.

The device allows the user to compensate for the parasitic resistance by increasing the voltage regulation set point according to the actual charge current and the resistance. For safe operation, the user should set the maximum allowed regulation voltage to REG06[4:2], and the minimum trace parasitic resistance (REG06[7:5]).

Equation 1.

8.3.3.4 Thermistor Qualification

The high capacity battery usually has two or more single cells in parallel. The device provides two TS pins to monitor the thermistor (NTC) in each cell independently.

8.3.3.4.1 Cold/Hot Temperature Window

The device continuously monitors battery temperature by measuring the voltage between the TS pins and ground, typically determined by a negative temperature coefficient thermistor and an external voltage divider. The device compares this voltage against its internal thresholds to determine if charging is allowed. To initiate a charge cycle, the battery temperature must be within the V_LTF to V_HTF thresholds. During the charge cycle the battery temperature must be within the V_LTF to V_TCO thresholds, else the device suspends charging and waits until the battery temperature is within the V_LTF to V_HTF range.

Figure 14. TS Resistor Network

When the TS fault occurs, the fault register REG09[2:0] indicates the actual condition on each TS pin and an INT is asserted to the host. The STAT pin indicates the fault when charging is suspended.

Figure 15. TS Pin Thermistor Sense Thresholds

Assuming a 103AT NTC thermistor is used on the battery pack Equation 2, the value RT1 and RT2 can be determined by using the following equation:

Equation 2.

Select 0°C to 45°C range for Li-ion or Li-polymer battery,
RTH_COLD = 27.28 kΩ
RTH_HOT = 4.911 kΩ
RT1 = 5.52 kΩ
RT2 = 31.23 kΩ

8.3.3.5 Charging Termination

The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is below termination current. After the charging cycle is complete, the BATFET turns off. The converter keeps running to power the system, and BATFET can turn back on to engage supplement mode.

When termination occurs, the status register REG08[5:4] is 11, and an INT is asserted to the host. Termination is temporarily disabled if the charger device is in input current/voltage regulation or thermal regulation. Termination can be disabled by writing 0 to REG05[7].

8.3.3.6 Charging Safety Timer

The device has safety timer to prevent extended charging cycle due to abnormal battery conditions. The safety timer is 2 hours when the battery is below BATLOWV threshold. The user can program fast charge safety timer through I2C (REG05[2:1]). When safety timer expires, the fault register REG09[5:4] goes 11 and an INT is asserted to the host. The safety timer feature can be disabled via I2C (REG05[3]). The following actions restart the safety timer:

The following actions restart the safety timer:

• At the beginning of a new charging cycle
• Toggle the CE pin HIGH to LOW to HIGH (charge enable)
• Write REG01[5:4] from 00 to 01 (charge enable)
• Write REG05[3] from 0 to 1 (safety timer enable)

During input voltage/current regulation, thermal regulation, or when FORCE_20PCT (REG02[0]) bit is set, , the safety timer counts at half clock rate since the actual charge current is likely to be below the register setting. For example, if the charger is in input current regulation (IINDPM) throughout the whole charging cycle, and the safety time is set to 5 hours, the safety timer will expire in 10 hours. This feature can be disabled by writing 0 to REG07[6].

It is recommended to disable safety timer first by clearing REG05[3] bit before safety timer configuraiton is changed. The safety timer can be re-enabled by setting REG05[3] bit.

8.3.3.7 USB Timer when Charging from USB100mA Source

The total charging time in default mode from USB100mA source is limited by a 45-min max timer. At the end of the timer, the device stops the converter and goes to HIZ.

8.3.4.1 Power Good Indicator (PG)

The PG in the device goes LOW to indicate a good input source when all of the following conditions are met:

• VBUS above UVLO
• VBUS above battery (not in sleep)
• VBUS below ACOV threshold
• VBUS above 3.8V when 30mA current is applied (not a poor source)

8.3.4.2 Charging Status Indicator (STAT)

The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED as the application diagram shows.

When a fault occurs, instead of blinking, the STAT pin in the charger device has a 10kΩ pulldown resistor to ground. When the pullup resistor is 30kΩ, the STAT voltage during fault is 1/4 of the pullup rail.

8.3.4.3 Interrupt to Host (INT)

In some applications, the host does not always monitor the charger operation. The INT notifies the system on the device operation. The following events will generate 256us INT pulse.

• USB/adapter source identified (through PSEL and OTG pins)
• Good input source detected
  • Not in sleep
  • Not in ACOV
  • Current limit above 30mA
• Input removed or ACOV
• Charge Complete
• Any FAULT event in REG09

When a fault occurs, the charger device sends out INT and latches the fault state in REG09 until the host reads the fault register. Before the host reads REG09, the charger device would not send any INT upon new faults except NTC fault (REG09[2:0]). The NTC fault is not latched and always reports the current thermistor conditions. To read the current fault status, the host has to read REG09 two times consecutively. The 1^st reads fault register status from the last INT and the 2^nd reads the current fault register status.

8.3.5.1 Input Current Limit on ILIM

For safe operation, the device has an additional hardware pin on ILIM to limit maximum input current on ILIM pin. The input maximum current is set by a resistor from ILIM pin to ground as:

Equation 3.

The actual input current limit is the lower value between ILIM setting and register setting (REG00[2:0]). For example, if the register setting is 111 for 3A, and ILIM has a 353Ω resistor to ground for 1.5A, the input current limit is 1.5A. ILIM pin can be used to set the input current limit rather than the register settings.

The device regulates ILIM pin at 1V. If ILIM voltage exceeds 1V, the device enters input current regulation (Refer to Dynamic Power Path Management section).

The voltage on ILIM pin is proportional to the input current. ILIM pin can be used to monitor the input current following Equation 4:

Equation 4.

For example, if ILIM pin sets 2A, and the ILIM voltage is 0.6V, the actual input current 1.2A. If ILIM pin is open, the input current is limited to zero since ILIM voltage floats above 1V. If ILIM pin is short, the input current limit is set by the register.

8.3.5.2 Thermal Regulation and Thermal Shutdown

The charger device monitors the internal junction temperature T_J to avoid overheat the chip and limits the IC surface temperature. When the internal junction temperature exceeds the preset limit (REG06[1:0]), the device lowers down the charge current. The wide thermal regulation range from 60°C to 120°C allows the user to optimize the system thermal performance.

During thermal regulation, the actual charging current is usually below the programmed battery charging current. Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register REG08[1] goes high.

Additionally, the device has thermal shutdown to turn off the converter. The fault register REG09[5:4] is 10 and an INT is asserted to the host.

8.3.5.3 Voltage and Current Monitoring in Buck Mode

The charger device closely monitors the input and system voltage, as well as HSFET and LSFET current for safe buck mode operation.

8.3.5.4 Overcurrent Protection in Boost Mode

The charger device closely monitors the Q1, Q2(HSFET) and Q3(LSFET) current to ensure safe boost mode operation. During overcurrent condition, the device will operate in hiccup mode for protection. While in hiccup mode cycle, the device turns off Q1 FET for t_{OTG_OCP_OFF} (32ms typical) and turns on Q1 FET for t_{OTG_OCP_ON}(100us typical) in an attempt to restart. If the overcurrent condition is removed, the boost converter will maintain the Q1 FET on state and the VBUS OTG output will operate normally. When overcurrent condition continues to exist, the device will repeat the hiccup cycle until overcurrent condition is removed.

8.3.5.5 Battery Protection

8.3.6.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each data bit transferred.

Figure 16. Bit Transfer on the I²C Bus

8.3.6.2 START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the master. The bus is considered busy after the START condition, and free after the STOP condition.

Figure 17. START and STOP conditions

8.3.6.3 Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data transfer then continues when the slave is ready for another byte of data and release the clock line SCL.

Figure 18. Data Transfer on the I²C Bus

8.3.6.4 Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9^th clock pulse, are generated by the master.

The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse.

When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then generate either a STOP to abort the transfer or a repeated START to start a new transfer.

8.3.6.5 Slave Address and Data Direction Bit

After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

Figure 19. Complete Data Transfer

8.3.6.5.1 Single Read and Write

Figure 20. Single Write

Figure 21. Single Read

If the register address is not defined, the charger IC send back NACK and go back to the idle state.

8.3.6.5.2 Multi-Read and Multi-Write

The charger device supports multi-read and multi-write on REG00 through REG08.

Figure 22. Multi-Write

Figure 23. Multi-Read

The fault register REG09 locks the previous fault and only clears it after the register is read. For example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG09 reports the fault when it is read the first time, but returns to normal when it is read the second time. To verify real time fault, the fault register REG09 should be read twice to get the real condition. In addition, the fault register REG09 does not support multi-read or multi-write.

8.4.1.1 Plug in USB 100mA Source with Good Battery

When the input source is detected as 100mA USB host, and the battery voltage is above batgood threshold (V_BATGD), the charger device enters HIZ state to meet the battery charging spec requirement.

If the charger device is in host mode, it will stay in HIZ state even after the USB100mA source is removed, and the adapter plugs in. During the HIZ state, REG00[7] is set HIGH and the system load is supplied from battery. It is recommended that the processor host always checks if the charger IC is in HIZ state when it wakes up. The host can write REG00[7] to 0 to exit HIZ state.

If the charger is in default mode, when the DC source is removed, the charger device will get out of HIZ state automatically. When the input source plugs in again, the charger IC runs detection on the input source and update the input current limit.

8.4.1.2 USB Timer when Charging from USB100mA Source

The total charging time in default mode from USB100mA source is limited by a 45-min max timer. At the end of the timer, the device stops the converter and goes to HIZ.

8.5.1.1 Input Source Control Register REG00 (reset = 00111000, or 3D)

8.5.1.2 Power-On Configuration Register REG01 (reset = 00011011, or 1B)

8.5.1.3 Charge Current Control Register REG02 (reset = 00100000, or 20)

8.5.1.4 Pre-Charge/Termination Current Control Register REG 03 (reset = 00010001, or 11)

8.5.1.5 Charge Voltage Control Register REG04 (reset = 10011010, or 9A)

8.5.1.6 Charge Termination/Timer Control Register REG05 (reset = 10011010, or 9A)

8.5.1.7 IR Compensation / Thermal Regulation Control Register REG06 (reset = 00000011, or 03)

8.5.1.8 Misc Operation Control Register REG07 (reset = 01001011, or 4B)

8.5.1.9 System Status Register REG08

8.5.1.10 Fault Register REG09

8.5.1.11 Vender / Part / Revision Status Register REG0A