SLUS977B September   2009  – August 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Overvoltage Protection
      2. 8.3.2 Input Overcurrent Protection
      3. 8.3.3 Battery Overvoltage Protection
      4. 8.3.4 Thermal Protection
      5. 8.3.5 Enable Function
      6. 8.3.6 PGATE Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 OPERATION Mode
      2. 8.4.2 POWER-DOWN Mode
      3. 8.4.3 POWER-ON RESET Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selection of RBAT
        2. 9.2.2.2 Selection of RCE
        3. 9.2.2.3 Selection of Input and Output Bypass Capacitors
        4. 9.2.2.4 Selection of the PGATE External MOSFET
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage IN, PGATE (with respect to VSS) –0.3 30 V
OUT (with respect to VSS) –0.3 12
ILIM, CE, VBAT (with respect to VSS) –0.3 7
Input current IN 2 A
Output current OUT 2 A
PGATE 5 mA
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
IN (IEC 61000-4-2)(3) Air Discharge ±15000
Contact ±8000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) With IN bypassed to the VSS with a 1-μF low-ESR ceramic capacitor

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage range 3.3 26 V
IIN Input current, IN pin 1.5 A
IOUT Output current, OUT pin 1.5 A
RILIM OCP programming resistor 31 kΩ
TJ Junction temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) bq24308 UNIT
DSG (WSON)
8 PINS
RθJA Junction-to-ambient thermal resistance 58.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 67.9 °C/W
RθJB Junction-to-board thermal resistance 29.7 °C/W
ψJT Junction-to-top characterization parameter 1.2 °C/W
ψJB Junction-to-board characterization parameter 30.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 7.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over junction temperature range –40°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IN
VUVLO Undervoltage lock-out, input power detected threshold CE= Low, VIN: 0 V → 3 V 2.5 2.7 2.8 V
VHYS-UVLO Hysteresis on UVLO CE= Low, VIN: 3 V → 0 V 200 260 300 mV
tDGL(PGOOD) Deglitch time, input power detected status CE = Low. Time measured from VIN
0V → 4 V 1 µs rise-time, to output turning ON		 8 ms
IDD Operating current CE= Low, VIN = 5 V, no load on OUT pin 410 500 μA
ISTDBY Standby current CE= High, VIN = 5 V 65 95 μA
INPUT TO OUTPUT CHARACTERISTICS
VDO Drop-out voltage IN to OUT CE = Low, VIN = 4 V, IOUT = 250 mA 45 75 mV
INPUT OVERVOLTAGE PROTECTION
VOVP Input overvoltage protection threshold CE= Low, VIN: 4 V to 10 V 6.1 6.3 6.5 V
VHYS-OVP Hysteresis on OVP CE= Low, VIN: 10 V to 4 V 20 60 110 mV
tPD(OVP) Input OVP propagation delay(1) CE= Low, Time measured from VIN 4 V → 10 V, 1µs rising time, to output turning OFF 0.2 1 μs
tON(OVP) Recovery time from input overvoltage condition CE = Low, Time measured from VIN
10 V → 4V, 1 µs fall-time, to output turning ON		 8 ms
OUTPUT VOLTAGE REGULATION
VO(REG) Output voltage CE = Low, VIN= 6 V, IOUT = 250 mA 4.85 5 5.15 V
INPUT OVERCURRENT PROTECTION
IOCP Internal input overcurrent protection threshold CE= Low, VIN = 5V, ILIM floating;
TJ = 0°C to 125°C		 630 700 770 mA
Input overcurrent protection range CE = Low, VIN = 5V; TJ = 0°C to 125°C 630 1500 mA
ΔIOCP OCP threshold accuracy TJ = 0°C to 125°C ±10%
TJ = –40°C to 125°C ±13%
KILIM Current limit programming: IOCP(program) = IOCP + KILIM ÷ RILIM 25000 AΩ
tBLANK(OCP) Blanking time, input overcurrent detected CE= Low 5 ms
tREC(OCP) Recovery time from input overcurrent condition CE = Low 64 ms
BATTERY OVERVOLTAGE PROTECTION
BVOVP Battery overvoltage protection threshold CE = Low, VIN > 4.4 V, VVBAT: 4.2 V → 4.5 V 4.3 4.35 4.40 V
VHYS-BOVP Hysteresis on BVOVP CE= Low, VIN > 4.4 V, VVBAT: 4.5 V → 3.9 V 200 275 320 mV
IVBAT Input bias current on VBAT pin VVBAT = 4.4 V, TJ = 25°C 10 nA
tDGL(BOVP) Deglitch time, battery overvoltage detected CE= Low, VIN > 4.4 V, time measured from VVBAT 4.2 V → 4.5 V, 1 µs rising time, to output turning OFF 176 µs
THERMAL PROTECTION
TJ(OFF) Thermal shutdown temperature 140 150 °C
TJ(OFF-HYS) Thermal shutdown hysteresis 20 °C
P-FET GATE DRIVER
VGCLMP Gate driver clamp voltage VIN > 17 V 13 15 17 V
LOGIC LEVELS ON CE
VIL Low-level input voltage 0 0.4 V
VIH High-level input voltage 1.4 V
IIL Low-level input current 1 μA
IIH High-level input current VCE = 1.8 V 15 μA
(1) Not tested in production. Specified by design.

7.6 Typical Characteristics

Test conditions (unless otherwise noted) for typical operating performance are: VIN = 5 V, CIN = 1 μF, COUT = 1 μF, RBAT = 100 kΩ, ROUT = 16 Ω, TA = 25°C (see Figure 12)
bq24308 vuvlo_ta_lus764.gif
Figure 1. Undervoltage Lockout vs Free-Air Temperature
bq24308 vovp_ta_lus977.gif
Figure 3. Regulation Voltage (OUT Pin) vs Free-Air Temperature
bq24308 iocp_ta_lus977.gif
Figure 5. OCP Threshold vs Free-Air Temperature
bq24308 ivbat_ta_lus977.gif
Figure 7. Leakage Current (BAT pin) vs Free-Air Temperature
bq24308 pv_vi_lus764.gif
Figure 9. PGATE Voltage vs Input Voltage
bq24308 vdo_ta_lus977.gif
Figure 2. Dropout Voltage (IN to OUT) vs Free-Air Temperature
bq24308 vovp2_ta_lus977.gif
Figure 4. OVP Threshold vs Free-Air Temperature
bq24308 bvop_ta_lus764.gif
Figure 6. Battery OVP Thresholds vs Free-Air Temperature
bq24308 idd_vin_lus977.gif
Figure 8. Supply Current vs Input Voltage