SLUS805C April   2008  – August 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Overvoltage Protection
      2. 7.3.2 Battery Overvoltage Protection
      3. 7.3.3 Thermal Protection
      4. 7.3.4 Start-Up Short-Circuit Protection
      5. 7.3.5 Enable Function
      6. 7.3.6 Fault Indication
    4. 7.4 Device Functional Modes
      1. 7.4.1 OPERATION Mode
      2. 7.4.2 POWER-DOWN Mode
      3. 7.4.3 POWER-ON RESET Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selection of R(BAT)
        2. 8.2.2.2 Selection of R(CE)
        3. 8.2.2.3 Selection of Input and Output Bypass Capacitors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) All voltage values are with respect to the network ground terminal unless otherwise noted.(1)
MIN MAX UNIT
VI Input voltage IN (with respect to VSS) –0.3 30 V
OUT (with respect to VSS) –0.3 12
FAULT, CE, VBAT (with respect to VSS) –0.3 7
IOUTmax Output source current OUT 2 A
Output sink current FAULT 15 mA
TJ Junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VI IN voltage range 3.3 30 V
IO Output current, OUT pin 1.7 A
TJ Junction temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) bq2438x UNIT
DSG (WSON)
8 PINS
RθJA Junction-to-ambient thermal resistance 64 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 84.1 °C/W
RθJB Junction-to-board thermal resistance 33.9 °C/W
ψJT Junction-to-top characterization parameter 1.9 °C/W
ψJB Junction-to-board characterization parameter 34.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 5.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Over junction temperature range –40°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IN
UVLO Undervoltage lock-out, input power
detected threshold		 CE = LO or HI, VIN: 0 V → 3 V 2.5 2.8 V
Vhys(UVLO) Hysteresis on UVLO CE = LO or HI, VIN: 3 V → 0 V 200 300 mV
IDD Operating current CE = LO, no load on OUT pin,
VIN = 5 V 		bq24380 250 μA
bq24381 300
bq24382 300
ISTDBY Standby current CE = HI, VIN = 5.5 V 100 μA
INPUT-TO-OUTPUT CHARACTERISTICS
VDO Dropout voltage IN to OUT CE = LO, VIN = 5 V, I(OUT) = 1 A 280 mV
IOFF Q1 off-state leakage current CE = HI, VIN = 5.5 V 10 μA
INPUT OVERVOLTAGE PROTECTION
VO(REG) Output voltage CE = LO, VIN = 6 V bq24380 5.3 5.5 5.7 V
bq24381 4.8 5 5.2
bq24382 4.8 5 5.2
VOVP Input overvoltage protection threshold CE = LO, VIN: 5 V → 8 V bq24380 6.1 6.3 6.5 V
bq24831 6.88 7.1 7.31
bq24382 10.17 10.5 10.83
Vhys(OVP) Hysteresis on OVP CE = LO or HI, VIN: 7 V → 5 V bq24380 25 110 mV
CE = LO or HI, VIN: 8 V → 5 V bq24831 25 120
bq24382 150 300
OUTPUT SHORT-CIRCUIT PROTECTION (ONLY at START-UP)
IO(SC) Short-circuit detection threshold 3 V < VIN < VOVP - Vhys(OVP) 1.3 1.5 1.7 A
tREC(SC) Retry interval if short-circuit detected 64 ms
BATTERY OVERVOLTAGE PROTECTION
BVOVP Battery overvoltage protection threshold VIN > 4.5 V, CE = LO 4.3 4.35 4.4 V
Vhys(BVovp) Hysteresis on BV(OVP) VIN > 4.5 V, CE = LO 200 320 mV
I(VBAT) Input bias current on VBAT pin TJ = 25°C 10 nA
THERMAL PROTECTION
TJ(OFF) Thermal shutdown temperature 140 150 °C
TJ(OFF-HYS) Thermal shutdown hysteresis 20 °C
LOGIC LEVELS ON CE
VIL Logic LOW input voltage 0 0.4 V
VIH Logic HIGH input voltage 1.4 V
IIL 1 μA
IIH VCE = 1.8 V 15 μA
LOGIC LEVELS ON FAULT
VOL Output LOW voltage ISINK = 5 mA 0.2 V
Ilkg Off-state leakage current, HI-Z VFAULT = 5 V 10 μA
(1) Not tested. Specified by design

6.6 Timing Requirements

MIN NOM MAX UNIT
IN
tDGL(PGOOD) Deglitch time, input power detected status CE = LO or HI. Time measured from
VIN 0 V → 5 V 1-μs rise-time		 8 ms
INPUT OVERVOLTAGE PROTECTION
tPD(OVP)(1) Input OV propagation delay VIN: 5 V → 10 V 200 ns
tREC(OVP) Recovery time from input overvoltage condition CE = LO. Time measured from
VIN: 7 V → 5 V, 1-μs fall-time		 8 ms
BATTERY OVERVOLTAGE PROTECTION
tDGL(BVovp) Deglitch time, battery overvoltage detected VIN > 4.5 V, CE = LO, Time measured from VVSAT rising from 4.1 V to 4.4 V to FAULT going low. 176 μs
bq24380 bq24381 bq24382 t_dia_lus805.gif
  1. Short-circuit during start-up
  2. Normal start-up condition
  3. Battery overvoltage event
  4. VUVLO < VIN < V(OREG) – VOUT tracks VIN
  5. Input overvoltage event
  6. Input below UVLO
  7. High-current event during normal operation
Figure 1. Timing Diagram

6.7 Typical Characteristics

bq24380 bq24381 bq24382 uvlo_ta_lus805.gif
Figure 2. UVLO vs Free-Air Temperature
bq24380 bq24381 bq24382 voreg_ta_lus805.gif
Figure 4. Output Voltage Regulation, VO(REG) vs Free-Air Temperature
bq24380 bq24381 bq24382 bovp_ta_lus805.gif
Figure 6. OVP Threshold, VBOVP vs Free-Air Temperature
bq24380 bq24381 bq24382 icc_vin_lus805.gif
Figure 8. Supply Current vs Input Voltage (bq24380)
bq24380 bq24381 bq24382 dov_ta_lus805.gif
Figure 3. Dropout Voltage vs Free-Air Temperature
bq24380 bq24381 bq24382 ovp_ta_lus805.gif
Figure 5. OVP Threshold vs Free-Air Temperature
bq24380 bq24381 bq24382 bat_lek_lus805.gif
Figure 7. Leakage Current (VBAT PIN) vs Free-Air Temperature
bq24380 bq24381 bq24382 icc_vin_81_lus805.gif
Figure 9. Supply Current vs Input Voltage (bq24381)