bq24600 Stand-Alone Synchronous Switch-Mode Li-Ion or Li-Polymer Battery Charger with Low Iq
- SLUS891B February 2010 – November 2014
  
  PRODUCTION DATA.

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DATA SHEET

bq24600 Stand-Alone Synchronous Switch-Mode Li-Ion or Li-Polymer Battery Charger with Low Iq

1 Features

1.2-MHz NMOS-NMOS Synchronous Buck Converter
Stand-Alone Charger Support for Li-Ion or Li-Polymer
5-V – 28-V VCC Input Voltage Range and Supports 1S-6S Battery Cells
Up to 10-A Charge Current and Adapter Current
High-Accuracy Voltage and Current Regulation
- ±0.5% Charge-Voltage Accuracy
- ±3% Charge-Current Accuracy
Integration
- Internal Loop Compensation
- Internal Soft Start
Safety
- Input Overvoltage Protection
- Battery Thermistor Sense Hot/Cold Charge Suspend
- Battery Detection
- Built-In Safety Timer
- Charge Overcurrent Protection
- Battery Short Protection
- Battery Overvoltage Protection
- Thermal Shutdown
Status Outputs
- Adapter Present
- Charger Operation Status
Charge Enable Pin
6-V Gate Drive for Synchronous Power Converter
30-ns Driver Dead-Time and 99.5% Max. Effective Duty Cycle
16-Pin 3.5-mm × 3.5-mm QFN package
Energy Star Low Quiescent Current I_q
- < 15-μA Off-State Battery Discharge Current
- < 1.5-mA Off-State Input Quiescent Current

2 Applications

Portable Equipment Handle Terminals
Industrial and Medical Equipment
Power Tools Appliance
Mobile Internet Device, and Ultra-Mobile PC

3 Description

The bq24600 is a highly integrated Li-ion or Li-polymer switch-mode battery-charge controller. It offers a constant-frequency synchronous PWM controller with high-accuracy charge current and voltage regulation, charge preconditioning, termination, and charge status monitoring,

The bq24600 charges the battery in three phases: preconditioning, constant current, and constant voltage. Charge is terminated when the current reaches a minimum level. An internal charge timer provides a safety backup. The bq24600 automatically restarts the charge cycle if the battery voltage falls below an internal threshold, and enters a low-quiescent-current sleep mode when the input voltage falls below the battery voltage.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
bq24600	VQFN (16)	3.50 mm x 3.50 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

4 Revision History

Changes from A Revision (October 2011) to B Revision

Changed Added Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Device and Documentation Go
Changed feature text From: "Supports 1-6 Battery Cells" To: "Supports 1S-6S Battery Cells"Go
Changed the Application list Go
Deleted the Table of Graphs from the Typical Characteristics section Go
Changed the Description of D3, D4 in Table 4 From: "LED diode, green, 2.1 V, 10 mΩ, Vishay-Dale, WSL2010R0100F" To:"LED diode, green, 2.1 V, 20 mA, LTST-C190GKT"Go

Changes from * Revision (February 2010) to A Revision

Changed descriptions of PH and BTST pins in Pin Description tableGo
Changed V_HTF to V_TCO in two places in Equation 5Go
Changed Equation 15Go

5 Pin Configuration and Functions

RVA Package

(Top View)

Pin Functions

PIN		I/O	FUNCTION DESCRIPTION
NAME	NO.	I/O	FUNCTION DESCRIPTION
VCC	1	I	IC power positive supply. Connect, through a 10-Ω resistor to the common-source (diode-OR) point: source of high-side P-channel MOSFET and source of reverse-blocking power P-channel MOSFET. Or connect through a 10-Ω resistor to the cathode of the input diode. Place a 1-μF ceramic capacitor from VCC to the GND pin close to the IC.
CE	2	I	Charge-enable active-HIGH logic input. HI enables charge. LO disables charge. It has an internal 1MΩ pull-down resistor.
STAT	3	I	Open-drain charge status pin to indicate various charger operation (See Table 2)
TS	4	I	Temperature qualification voltage input for battery pack negative temperature coefficient thermistor. Program the hot and cold temperature window with a resistor divider from VREF to TS to GND.
PG	5	O	Open-drain power-good status output. The transistor turns on when a valid VCC is detected. It is turned off in the sleep mode. PG can be used to drive an LED or communicate with a host processor. It can be used to drive ACFET and BATFET.
VREF	6	O	3.3-V regulated voltage output. Place a 1-μF ceramic capacitor from VREF to the GND pin close to the IC. This voltage could be used for programming of voltage and current regulation and for programming the TS threshold.
ISET	7	I	Charge current set input. The voltage of ISET pin programs the charge current regulation, pre-charge current and termination current set-point.
VFB	8	O	Output voltage analog feedback adjustment. Connect the output of a resistive voltage divider from the battery terminals to this node to adjust the output battery regulation voltage.
SRN	9	I	Charge-current sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from SRN pin to GND for common-mode filtering.
SRP	10	I	Charge-current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from SRP pin to GND for common-mode filtering.
GND	11	--	Low-current sensitive analog/digital ground. On PCB layout, connect with thermal pad underneath the IC.
REGN	12	O	PWM low-side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from REGN to the PGND pin, close to the IC. Use for low-side driver and high-side driver bootstrap voltage by connecting a small-signal Schottky diode from REGN to BTST.
LODRV	13	O	PWM low-side driver output. Connect to the gate of the low-side power MOSFET with a short trace.
PH	14	I	PWM high-side driver negative supply. Connect to the phase-switching node (junction of the low-side power MOSFET drain, high-side power MOSFET source, and output inductor).
HIDRV	15	O	PWM high-side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
BTST	16	I	PWM high-side driver negative supply. Connect the 0.1-μF bootstrap capacitor from PH to BTST, and a bootstrap Schottky diode from REGN to BTST.
Thermal pad	--	--	Exposed pad beneath the IC. Always solder thermal pad to the board, and have vias on the thermal pad plane star-connecting to GND and ground plane for high-current power converter. It also serves as a thermal pad to dissipate the heat.

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾⁽³⁾

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Voltage range	VCC, SRP, SRN, CE, STAT, PG	–0.3	33	V
	PH	–2	36	V
	VFB	–0.3	16	V
	REGN, LODRV, TS	–0.3	7	V
	BTST, HIDRV with respect to GND	–0.3	39	V
	VREF, ISET	–0.3	3.6	V
Maximum difference voltage	SRP–SRN	–0.5	0.5	V
Junction temperature range, T_J		–40	155	ºC

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the data book for thermal limitations and considerations of packages.

(3) Must have a series resistor between battery pack and VFB if battery-pack voltage is expected to be greater than 16 V. Usually the resistor-divider top resistor takes care of this.

6.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–55	155	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	–1000	1000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	–250	250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

		VALUE	UNIT
Voltage range	VCC, SRP, SRN, CE, STAT, PG	–0.3 to 28	V
	PH	–2 to 30	V
	VFB	–0.3 to 14	V
	REGN, LODRV, TS	–0.3 to 6.5	V
	BTST, HIDRV with respect to GND	–0.3 to 34	V
	ISET	–0.3 to 3.3	V
	VREF	3.3	V
Maximum difference voltage	SRP–SRN	–0.2 to 0.2	V
Junction temperature range, T_J		0 to 125	ºC

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		RVA	UNIT
THERMAL METRIC⁽¹⁾		16 PINS	UNIT
R_θJA	Junction-to-ambient thermal resistance	43.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	81
R_θJB	Junction-to-board thermal resistance	16
ψ_JT	Junction-to-top characterization parameter	0.6
ψ_JB	Junction-to-board characterization parameter	15.77
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	4

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

5 V ≤ V_VCC ≤ 28 V, 0°C < T_J < 125°C, typical values are at T_A = 25°C, with respect to GND (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
OPERATING CONDITIONS
V_{VCC_OP}	VCC input voltage operating range		5		28	V
QUIESCENT CURRENTS
I_BAT	Total battery discharge current (sum of currents into VCC, BTST, PH, SRP, SRN, VFB), VFB ≤ 2.1 V	V_VCC < V_SRN, V_VCC > V_UVLO (SLEEP)			15	μA
I_AC	Adapter supply current (current into VCC pin)	V_VCC > V_SRN, V_VCC > V_UVLO CE = LOW (IC quiescent current)		1	1.5	mA
		V_VCC > V_SRN, V_VCC >V_VCCLOW, CE = HIGH, charge done		2	5
		V_VCC > V_SRN, V_VCC >V_VCCLOW, CE = HIGH, Charging, Qg_total = 20 nC, V_VCC= 20 V		50
CHARGE VOLTAGE REGULATION
V_FB	Feedback regulation voltage			2.1		V
	Charge voltage regulation accuracy	T_J = 0°C to 85°C	–0.5%		0.5%
	Charge voltage regulation accuracy	T_J = –40°C to 125°C	–0.7%		0.7%
I_VFB	Leakage Current into VFB pin	VFB = 2.1 V			100	nA
CURRENT REGULATION – FAST CHARGE
V_ISET	ISET voltage range				2	V
V_{IREG_CHG}	SRP-SRN current sense voltage range	V_{IREG_CHG} = V_SRP – V_SRN			100	mV
K_ISET	Charge current set factor (amps of charge current per volt on ISET pin)	R_SENSE = 10 mΩ		5		A/V
	Charge current regulation accuracy	V_{IREG_CHG} = 40 mV	–3%		3%
		V_{IREG_CHG} = 20 mV	–4%		4%
		V_{IREG_CHG} = 5 mV	–25%		25%
		V_{IREG_CHG} = 1.5 mV (V_SRN > 3.1 V)	–40%		40%
I_ISET	Leakage current into ISET pin	V_ISET = 2 V			100	nA
CURRENT REGULATION – PRECHARGE
	Precharge current range	R_SENSE = 10 mΩ		I_CHARGE/10		A
K_PRECH	Precharge current set factor (amps of precharge current per volt on ISET pin)	R_SENSE = 10 mΩ		0.5		A/V
	Precharge current regulation accuracy	V_{IREG_PRECH} = 10 mV	–10%		10%
		V_{IREG_PRECH} = 5 mV	–25%		25%
		V_{IREG_PRECH} = 1.5 mV (V_SRN < 3.1 V)	–55%		55%
CHARGE TERMINATION
	Termination current range	R_SENSE = 10 mΩ		I_CHARGE/10		A
K_TERM	Termination current set factor (amps of termination current per volt on ISET pin)	R_SENSE = 10 mΩ		0.5		A/V
	Termination current accuracy	V_ITERM = 10 mV	–10%		10%
		V_ITERM = 5 mV	–25%		25%
		V_ITERM = 1.5 mV	–45%		45%
I_QUAL	Termination qualification current	Discharge current once termination is detected		2		mA
INPUT UNDERVOLTAGE LOCKOUT COMPARATOR (UVLO)
V_UVLO	AC undervoltage rising threshold	Measure on VCC	3.65	3.85	4	V
V_{UVLO_HYS}	AC undervoltage hysteresis, falling			350		mV
VCC LOWV COMPARATOR
	Falling threshold, disable charge	Measure on VCC		4.1		V
	Rising threshold, resume charge			4.35	4.5	V
SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)
V_{SLEEP _FALL}	SLEEP falling threshold	V_VCC – V_SRN to enter SLEEP	40	100	150	mV
V_{SLEEP_HYS}	SLEEP hysteresis			500		mV
BAT LOWV COMPARATOR
V_LOWV	Precharge to fast-charge transition (LOWV threshold)	Measured on VFB pin	1.534	1.55	1.566	V
V_{LOWV_HYS}	LOWV hysteresis			100		mV
RECHARGE COMPARATOR
V_RECHG	Recharge threshold (with respect to.V_REG)	Measured on VFB pin	35	50	65	mV
BAT OVER-VOLTAGE COMPARATOR
V_{OV_RISE}	Overvoltage rising threshold	As percentage of VFB		104%
V_{OV_FALL}	Overvoltage falling threshold	As percentage of VFB		102%
INPUT OVER-VOLTAGE COMPARATOR (ACOV)
V_ACOV	AC overvoltage rising threshold on VCC		31.04	32	32.96	V
V_{ACOV_HYS}	AC overvoltage falling hysteresis			1		V
THERMAL SHUTDOWN COMPARATOR
T_SHUT	Thermal shutdown rising temperature	Temperature increasing		145		°C
T_{SHUT_HYS}	Thermal shutdown hysteresis			15		°C
THERMISTOR COMPARATOR
V_LTF	Cold temperature rising threshold	As percentage to V_VREF	72.5%	73.5%	74.5%
V_{LTF_HYS}	Rising hysteresis	As percentage to V_VREF	0.2%	0.4%	0.6%
V_HTF	Hot temperature rising threshold	As percentage to V_VREF	36.2%	37%	37.8%
V_TCO	Cutoff temperature rising threshold	As percentage to V_VREF	33.7%	34.4%	35.1%
	Deglitch time for temperature out of range detection	V_TS > V_LTF, or V_TS < V_TCO, or V_TS < V_HTF		400		ms
	Deglitch time for temperature in valid range detection	V_TS < V_LTF – V_{LTF_HYS} or V_TS >V_TCO, or V_TS > V_HTF		20		ms
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
V_OC	Charge overcurrent falling threshold	Current rising, in non-synchronous mode, mesure on V_(SRP-SRN), V_SRP < 2 V		45.5		mV
	Charge overcurrent falling threshold	Current rising, as percentage of V_{(IREG_CHG)}, in synchronous mode, V_SRP > 2.2 V		160%
	Charge overcurrent threshold floor	Minimum OCP threshold in synchronous mode, measure on V_(SRP-SRN), V_SRP > 2.2 V		50		mV
	Charge over-current threshold ceiling	Maximum OCP threshold in synchronous mode, measure on V_(SRP-SRN), V_SRP > 2.2 V		180		mV
CHARGE UNDERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
V_ISYNSET	Charge under-current falling threshold	V_SRP>2.2 V, switch from CCM to DCM	1	5	9	mV
BATTERY SHORTED COMPARATOR (BATSHORT)
V_BATSHT	BAT Short falling threshold, forced non-syn mode	V_SRP falling		2		V
V_{BATSHT_HYS}	BAT short rising hysteresis			200		mV
LOW CHARGE CURRENT COMPARATOR
V_LC	Low charge current (average) falling threshold to force into non-sync mode	Measure V_(SRP-SRN)		1.25		mV
V_{LC_HYS}	Low charge current rising hysteresis			1.25		mV
VREF REGULATOR
V_{VREF_REG}	VREF regulator voltage	V_VCC > V_UVLO (0 - 35-mA load)	3.267	3.3	3.333	V
I_{VREF_LIM}	VREF current limit	V_VREF = 0 V, V_VCC > V_UVLO	35			mA
REGN REGULATOR
V_{REGN_REG}	REGN regulator voltage	V_VCC > 10 V, CE = HIGH (0 - 40 mA load)	5.7	6.0	6.3	V
I_{REGN_LIM}	REGN current limit	V_REGN = 0 V, V_VCC> V_UVLO	40			mA
BATTERY DETECTION
I_WAKE	Wake current	R_SENSE = 10 mΩ	50	125	200	mA
I_DISCHARGE	Discharge current			8		mA
I_FAULT	Fault current after a timeout fault			2		mA
V_WAKE	Wake threshold (relative to V_REG)	Voltage on VFB to detect battery absent during wake		50		mV
V_DISCH	Discharge threshold	Voltage on VFB to detect battery absent during discharge		1.55		V
PWM HIGH SIDE DRIVER (HIDRV)
R_{DS_HI_ON}	High-side driver (HSD) turnon resistance	V_BTST – V_PH = 5.5 V		3.3	6	Ω
R_{DS_HI_OFF}	High-side driver turnoff resistance	V_BTST – V_PH = 5.5 V		1	1.3	Ω
V_{BTST_REFRESH}	Bootstrap refresh comparator threshold voltage	V_BTST – V_PH when low side refresh pulse is requested	4	4.2		V
PWM LOW SIDE DRIVER (LODRV)
R_{DS_LO_ON}	Low-side driver (LSD) turnon resistance			4.1	7	Ω
R_{DS_LO_OFF}	Low-side driver turnoff resistance			1	1.4	Ω
PWM OSCILLATOR
V_{RAMP_HEIGHT}	PWM ramp height	As percentage of VCC		7%
	PWM switching frequency⁽¹⁾		1020	1200	1380	kHz
INTERNAL SOFT START (8 steps to regulation current I_CHARGE)
	Soft-start steps			8		step
CHARGER SECTION POWER-UP SEQUENCING
	Charge-enable delay after power up	Delay from when CE = 1 to when the charger is allowed to turn on		1.5		s
LOGIC IO PIN CHARACTERISTICS (CE, STAT, PG)
V_{IN_LO}	CE input low threshold voltage				0.8	V
V_{IN_HI}	CE input high threshold voltage		2.1
V_{BIAS_CE}	CE input bias current	V = 3.3 V (CE has internal 1MΩ pulldown resistor)			6	μA
V_{OUT_LO}	STAT, PG output low saturation voltage	Sink current = 5 mA			0.5	V
I_{OUT_HI}	Leakage current	V = 32 V			1.2	µA

(1) Specified by design.

6.6 Timing Requirements

			MIN	TYP	MAX	UNIT
CHARGE TERMINATION
	Deglitch time for termination (both edges)			100		ms
t_QUAL	Termination qualification time	V_BAT > V_RECH and I_CHARGE < I_TERM		250		ms
SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)
	SLEEP rising delay	VCC falling below SRN, delay to pull up PG		1		µs
	SLEEP falling delay	VCC rising above SRN, delay to pull down PG		30		ms
	SLEEP rising shutdown deglitch	VCC falling below SRN, delay to enter SLEEP mode		100		ms
	SLEEP falling powerup deglitch	VCC rising above SRN, delay to come out of SLEEP mode		30		ms
BAT LOWV COMPARATOR
	LOWV rising deglitch	VFB falling below V_LOWV			25	ms
	LOWV falling deglitch	VFB rising above V_LOWV + V_{LOWV_HYS}			25	ms
RECHARGE COMPARATOR
	Recharge rising deglitch	VFB decreasing below V_RECHG		10		ms
	Recharge falling deglitch	VFB increasing above V_RECHG		10		ms
INPUT OVER-VOLTAGE COMPARATOR (ACOV)
V_{ACOV_HYS}	AC overvoltage rising deglitch			1		ms
	AC overvoltage falling deglitch			1		ms
THERMISTOR COMPARATOR
	Thermal shutdown rising deglitch	Temperature increasing		100		μs
	Thermal shutdown falling deglitch	Temperature decreasing		10		ms
BATTERY SHORTED COMPARATOR (BATSHORT)
V_{BATSHT_DEG}	Deglitch on both edges			1		μs
LOW CHARGE CURRENT COMPARATOR
V_{LC_DEG}	Deglitch on both edges			1		μs
SAFETY TIMER
t_PRECHG	Precharge safety timer range⁽¹⁾	Precharge time before fault occurs	1440	1800	2160	s
t_CHARGE	Internal five hour safety timer⁽¹⁾		4.25	5	5.75	hr
BATTERY DETECTION
t_WAKE	Wake timer	Max time charge is enabled		500		ms
t_DISCHARGE	Discharge timer	Max time discharge current is applied		1		s
PWM DRIVERS TIMING
	Driver dead time	Dead time when switching between LSD and HSD, no load at LSD and HSD		30		ns
INTERNAL SOFT START (8 steps to regulation current I_CHARGE)
	Soft-start step time			1.6		ms

6.7 Typical Characteristics

CE = 1

Figure 1. REF REGN and PG Power Up

Figure 3. Charge Disable

Figure 2. Charge Enable

Figure 4. Battery-to-GND Short Protection