SLUSA44A March   2010  – July 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Voltage Regulation
      2. 7.3.2  Output Current Regulation
      3. 7.3.3  Power Up
      4. 7.3.4  Enable and Disable Charging
      5. 7.3.5  Automatic Internal Soft-Start Charger Current
      6. 7.3.6  Converter Operation
      7. 7.3.7  Synchronous and Nonsynchronous Operation
      8. 7.3.8  Input Overvoltage Protection (ACOV)
      9. 7.3.9  Output Overvoltage Protection
      10. 7.3.10 Cycle-by-Cycle Charge Overcurrent Protection
      11. 7.3.11 Thermal Shutdown Protection
      12. 7.3.12 Temperature Qualification
      13. 7.3.13 CE (Charge Enable)
      14. 7.3.14 PG Output
      15. 7.3.15 Charge Status Outputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Constant Current Mode
      2. 7.4.2 Constant Voltage Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 Input Capacitor
        3. 8.2.2.3 Output Capacitor
        4. 8.2.2.4 Power MOSFETs Selection
        5. 8.2.2.5 Input Filter Design
        6. 8.2.2.6 Inductor, Capacitor, and Sense Resistor Selection Guidelines
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RVA Package
16-Pin VQFN With Exposed Thermal Pad
Top View
bq24640 po2_lusa44.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
BTST 16 P PWM high-side driver positive supply. Connect the 0.1-μF bootstrap capacitor from PH to BTST.
CE 2 I Charge enable, active HIGH logic input. HI enables charge, and LO disables charge. Connect to pullup rail with 10-kΩ resistor. It has an internal 1-MΩ pulldown resistor.
GND 11 P Low-current sensitive analog/digital ground. On PCB layout, connect with thermal pad underneath the IC.
HIDRV 15 O PWM high-side driver output. Connect to the gate of the high-side N-channel power MOSFET with a short trace.
ISET 7 I Charge current set point. The voltage is set through a voltage divider from VREF to ISET and to GND.
bq24640 IEQ1_ichg_lusa44.gif
LODRV 13 O PWM low-side driver output. Connect to the gate of the low-side N-channel power MOSFET with a short trace.
PG 5 O Open-drain active-low adapter status output. Connect to pullup rail through LED and 10-kΩ resistor. The LED turns on when a valid is detected, and off in the sleep mode.
PH 14 P Switching node, charge current output inductor connection. Connect the 0.1-μF bootstrap capacitor from PH to BTST.
REGN 12 P PWM low-side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from REGN to GND pin close to the IC. Use for low-side driver and high-side driver bootstrap voltage by small signal Schottky diode from REGN to BTST.
SRN 9 I Charge current-sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from SRN pin to GND for common-mode filtering.
SRP 10 P/I Charge current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from SRP pin to GND for common-mode filtering.
STAT 3 O Open-drain charge status output to indicate various charger operation. Connect to the pullup rail through the LED and 10-kΩ (see Table 4).
TS 4 I Temperature qualification voltage input for negative temperature coefficient thermistor. Program the hot and cold temperature window with a resistor-divider from VREF to TS to GND. Recommend SEMITEC 103AT-2 10-kΩ thermister.
VCC 1 P IC power positive supply. Connect through a 10-Ω resistor to the cathode of input diode. Place a 1-μF ceramic capacitor from VCC to GND and place it as close as possible to IC to filter out the noise.
VFB 8 I Charge voltage analog feedback adjustment. Connect a resistor divider from output to VFB to GND to adjust the output voltage. The internal regulation limit is 2.1V.
VREF 6 P 3.3-V reference voltage output. Place a 1-μF ceramic capacitor from VREF to GND pin close to the IC. This voltage could be used for programming charge current regulation on ISET and for thermal threshold on TS. It can be used as the pullup rail of STAT, and PG.
Thermal pad — Exposed pad beneath the IC. Always solder thermal pad to the board, and have vias on the thermal pad plane star-connecting to GND and ground plane for high-current power converter. It also serves as a thermal pad to dissipate the heat.
(1) P - Power, I - Input, O - Output