SLUSAL0C September   2011  – January 2020 BQ24725A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 SMBus Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1  Adapter Detect and ACOK Output
      2. 8.4.2  Adapter Over Voltage (ACOVP)
      3. 8.4.3  System Power Selection
      4. 8.4.4  Battery LEARN Cycle
      5. 8.4.5  Enable and Disable Charging
      6. 8.4.6  Automatic Internal Soft-Start Charger Current
      7. 8.4.7  High Accuracy Current Sense Amplifier
      8. 8.4.8  Charge Timeout
      9. 8.4.9  Converter Operation
      10. 8.4.10 Continuous Conduction Mode (CCM)
      11. 8.4.11 Discontinuous Conduction Mode (DCM)
      12. 8.4.12 Input Over Current Protection (ACOC)
      13. 8.4.13 Charge Over Current Protection (CHGOCP)
      14. 8.4.14 Battery Over Voltage Protection (BATOVP)
      15. 8.4.15 Battery Shorted to Ground (BATLOWV)
      16. 8.4.16 Thermal Shutdown Protection (TSHUT)
      17. 8.4.17 EMI Switching Frequency Adjust
      18. 8.4.18 Inductor Short, MOSFET Short Protection
    5. 8.5 Register Maps
      1. 8.5.1 Battery-Charger Commands
      2. 8.5.2 Setting Charger Options
        1. Table 3. Charge Options Register (0x12H)
      3. 8.5.3 Setting the Charge Current
        1. Table 4. Charge Current Register (0x14H), Using 10mΩ Sense Resistor
      4. 8.5.4 Setting the Charge Voltage
        1. Table 5. Charge Voltage Register (0x15H)
      5. 8.5.5 Setting Input Current
        1. Table 6. Input Current Register (0x3FH), Using 10mΩ Sense Resistor
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical System with Two NMOS Selector
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Negative Output Voltage Protection
          2. 9.2.1.2.2 Reverse Input Voltage Protection
          3. 9.2.1.2.3 Reduce Battery Quiescent Current
          4. 9.2.1.2.4 Inductor Selection
          5. 9.2.1.2.5 Input Capacitor
          6. 9.2.1.2.6 Output Capacitor
          7. 9.2.1.2.7 Power MOSFETs Selection
          8. 9.2.1.2.8 Input Filter Design
          9. 9.2.1.2.9 BQ24725A Design Guideline
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Simplified System without Power Path
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.9 Converter Operation

The synchronous buck PWM converter uses a fixed frequency voltage mode control scheme and internal type III compensation network. The LC output filter gives a characteristic resonant frequency

Equation 1. BQ24725A eq3_lusa79.gif

The resonant frequency fo is used to determine the compensation to ensure there is sufficient phase margin and gain margin for the target bandwidth. The LC output filter should be selected to give a resonant frequency of 10–20 kHz nominal for the best performance. Suggest component value as charge current of 750kHz default switching frequency is shown in Table 1.

Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point.

Table 1. Suggest Component Value as Charge Current of Default 750kHz Switching Frequency

Charge Current 2A 3A 4A 6A 8A
Output Inductor Lo (µH) 6.8 or 8.2 5.6 or 6.8 3.3 or 4.7 3.3 2.2
Output Capacitor Co (µF) 20 20 20 30 40
Sense Resistor (mΩ) 10 10 10 10 10

The BQ24725A has three loops of regulation: input current, charge current and charge voltage. The three loops are brought together internally at the error amplifier. The maximum voltage of the three loops appears at the output of the error amplifier EAO. An internal saw-tooth ramp is compared to the internal error control signal EAO (see Figure 10) to vary the duty-cycle of the converter. The ramp has offset of 200mV in order to allow 0% duty-cycle.

When the battery charge voltage approaches the input voltage, EAO signal is allowed to exceed the saw-tooth ramp peak in order to get a 100% duty-cycle. If voltage across BTST and PHASE pins falls below 4.3V, a refresh cycle starts and low-side n-channel power MOSFET is turned on to recharge the BTST capacitor. It can achieve duty cycle of up to 99.5%.