SLUSAL0C September   2011  – January 2020 BQ24725A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 SMBus Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1  Adapter Detect and ACOK Output
      2. 8.4.2  Adapter Over Voltage (ACOVP)
      3. 8.4.3  System Power Selection
      4. 8.4.4  Battery LEARN Cycle
      5. 8.4.5  Enable and Disable Charging
      6. 8.4.6  Automatic Internal Soft-Start Charger Current
      7. 8.4.7  High Accuracy Current Sense Amplifier
      8. 8.4.8  Charge Timeout
      9. 8.4.9  Converter Operation
      10. 8.4.10 Continuous Conduction Mode (CCM)
      11. 8.4.11 Discontinuous Conduction Mode (DCM)
      12. 8.4.12 Input Over Current Protection (ACOC)
      13. 8.4.13 Charge Over Current Protection (CHGOCP)
      14. 8.4.14 Battery Over Voltage Protection (BATOVP)
      15. 8.4.15 Battery Shorted to Ground (BATLOWV)
      16. 8.4.16 Thermal Shutdown Protection (TSHUT)
      17. 8.4.17 EMI Switching Frequency Adjust
      18. 8.4.18 Inductor Short, MOSFET Short Protection
    5. 8.5 Register Maps
      1. 8.5.1 Battery-Charger Commands
      2. 8.5.2 Setting Charger Options
        1. Table 3. Charge Options Register (0x12H)
      3. 8.5.3 Setting the Charge Current
        1. Table 4. Charge Current Register (0x14H), Using 10mΩ Sense Resistor
      4. 8.5.4 Setting the Charge Voltage
        1. Table 5. Charge Voltage Register (0x15H)
      5. 8.5.5 Setting Input Current
        1. Table 6. Input Current Register (0x3FH), Using 10mΩ Sense Resistor
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical System with Two NMOS Selector
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Negative Output Voltage Protection
          2. 9.2.1.2.2 Reverse Input Voltage Protection
          3. 9.2.1.2.3 Reduce Battery Quiescent Current
          4. 9.2.1.2.4 Inductor Selection
          5. 9.2.1.2.5 Input Capacitor
          6. 9.2.1.2.6 Output Capacitor
          7. 9.2.1.2.7 Power MOSFETs Selection
          8. 9.2.1.2.8 Input Filter Design
          9. 9.2.1.2.9 BQ24725A Design Guideline
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Simplified System without Power Path
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RGR Package
20-Pin VQFN
Top View
BQ24725A po_lusaL0.gif

Pin Functions

PIN DESCRIPTION
NO. NAME
1 ACN Input current sense resistor negative input. Place an optional 0.1µF ceramic capacitor from ACN to GND for common-mode filtering. Place a 0.1µF ceramic capacitor from ACN to ACP to provide differential mode filtering.
2 ACP Input current sense resistor positive input. Place a 0.1µF ceramic capacitor from ACP to GND for common-mode filtering. Place a 0.1µF ceramic capacitor from ACN to ACP to provide differential-mode filtering.
3 CMSRC ACDRV charge pump source input. Place a 4kΩ resistor from CMSRC to the common source of ACFET (Q1) and RBFET (Q2) limits the in-rush current on CMSRC pin.
4 ACDRV Charge pump output to drive both adapter input n-channel MOSFET (ACFET) and reverse blocking n-channel MOSFET (RBFET). ACDRV voltage is 6V above CMSRC when voltage on ACDET pin is between 2.4V to 3.15V, voltage on VCC pin is above UVLO and voltage on VCC pin is 275mV above voltage on SRN pin so that ACFET and RBFET can be turned on to power the system by AC adapter. Place a 4kΩ resistor from ACDRV to the gate of ACFET and RBFET limits the in-rush current on ACDRV pin.
5 ACOK AC adapter detection open drain output. It is pulled HIGH to external pull-up supply rail by external pull-up resistor when voltage on ACDET pin is between 2.4V and 3.15V, and voltage on VCC is above UVLO and voltage on VCC pin is 275mV above voltage on SRN pin, indicating a valid adapter is present to start charge. If any one of the above conditions can not meet, it is pulled LOW to GND by internal MOSFET. Connect a 10kΩ pull up resistor from ACOK to the pull-up supply rail.
6 ACDET Adapter detection input. Program adapter valid input threshold by connecting a resistor divider from adapter input to ACDET pin to GND pin. When ACDET pin is above 0.6V and VCC is above UVLO, REGN LDO is present, ACOK comparator and IOUT are both active.
7 IOUT Buffered adapter or charge current output, selectable with SMBus command ChargeOption(). IOUT voltage is 20 times the differential voltage across sense resistor. Place a 100pF or less ceramic decoupling capacitor from IOUT pin to GND.
8 SDA SMBus open-drain data I/O. Connect to SMBus data line from the host controller or smart battery. Connect a 10kΩ pull-up resistor according to SMBus specifications.
9 SCL SMBus open-drain clock input. Connect to SMBus clock line from the host controller or smart battery. Connect a 10kΩ pull-up resistor according to SMBus specifications.
10 ILIM Charge current limit input. Program ILIM voltage by connecting a resistor divider from system reference 3.3V rail to ILIM pin to GND pin. The lower of ILIM voltage or DAC limit voltage sets charge current regulation limit. To disable the control on ILIM, set ILIM above 1.6V. Once voltage on ILIM pin falls below 75mV, charge is disabled. Charge is enabled when ILIM pin rises above 105mV.
11 BATDRV Charge pump output to drive Battery to System n-channel MOSFET (BATFET). BATDRV voltage is 6V above SRN to turn on BATFET to power the system from battery. BATDRV voltage is SRN voltage to turn off BATFET to power system from AC adapter. Place a 4kΩ resistor from BATDRV to the gate of BATFET limits the in-rush current on BATDRV pin.
12 SRN Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well. Connect SRN pin to a 7.5 Ω resistor first then from resistor another terminal connect a 0.1µF ceramic capacitor to GND for common-mode filtering and connect to current sensing resistor. Connect a 0.1µF ceramic capacitor between current sensing resistor to provide differential mode filtering. See application information about negative output voltage protection for hard shorts on battery to ground or battery reverse connection by adding small resistor.
13 SRP Charge current sense resistor positive input. Connect SRP pin to a 10 Ω resistor first then from resistor another terminal connect to current sensing resistor. Connect a 0.1µF ceramic capacitor between current sensing resistor to provide differential mode filtering. See application information about negative output voltage protection for hard shorts on battery to ground or battery reverse connection by adding small resistor.
14 GND IC ground. On PCB layout, connect to analog ground plane, and only connect to power ground plane through the power pad underneath IC.
15 LODRV Low side power MOSFET driver output. Connect to low side n-channel MOSFET gate.
16 REGN Linear regulator output. REGN is the output of the 6V linear regulator supplied from VCC. The LDO is active when voltage on ACDET pin is above 0.6V and voltage on VCC is above UVLO. Connect a 1µF ceramic capacitor from REGN to GND.
17 BTST High side power MOSFET driver power supply. Connect a 0.047µF capacitor from BTST to PHASE, and a bootstrap Schottky diode from REGN to BTST.
18 HIDRV High side power MOSFET driver output. Connect to the high side n-channel MOSFET gate.
19 PHASE High side power MOSFET driver source. Connect to the source of the high side n-channel MOSFET.
20 VCC Input supply, diode OR from adapter or battery voltage. Use 10Ω resistor and 1µF capacitor to ground as low pass filter to limit inrush current.
PowerPAD™ Exposed pad beneath the IC. Analog ground and power ground star-connected only at the PowerPAD plane. Always solder PowerPad to the board, and have vias on the PowerPAD plane connecting to analog ground and power ground planes. It also serves as a thermal pad to dissipate the heat.