8.3.1 Adapter Detect and Power Up

An external resistor voltage divider attenuates the adapter voltage before it goes to ACIN. The adapter detect threshold should typically be programmed to a value greater than the maximum battery voltage and lower than the minimum allowed adapter voltage. The ACIN divider should be placed before the input power path selector in order to sense the true adapter input voltage.

If DCINA is below 4 V, the device is disabled.

If ACIN is below 0.6 V but DCINA is above 4.5 V, ACOK and VICM are disabled and pulled down to GND. The total quiescent current is less than 10 µA.

Once ACIN rises above 0.6 V and DCINA is above 4.5 V, VREF goes to 3.3 V and all the bias circuits are enabled, ACOK low indicated ACIN is still below 2.4 V and the valid adaptor is not available. VICM becomes valid to proportionally reflect the adapter current.

When ACIN keeps rising and passes 2.4 V, a valid AC adapter is present. 100 µs later, the following occurs:

• ACOK becomes high through external pull-up resistor to the VREF rail
• Charger turns on if all the conditions are satisfied (refer to )

8.3.2 Enable and Disable Charging

The following conditions must be valid before charging is enabled:

• Not in UVLO (DCINA > 4.5 V, and VDDSMB > 2.5 V)
• Adapter is detected (ACIN > 2.4 V)
• Adapter – Battery voltage is higher than V(DCINA-VFB) Comparator threshold
• SMBus ChargeVoltage(),ChargeCurrent(), and InputCurrent() DAC registers are inside the valid range
• CE is HIGH
• 2 ms delay is complete after adapter detected and CE goes high
• VDDP and VREF are valid
• Not in Thermal Shutdown (TSHUT)

One of the following conditions will stop the on-going charging:

• SMBus ChargeVoltage(),ChargeCurrent(), or InputCurrent() DAC registers are outside the valid range
• CE is LOW
• Adapter is removed; (DCINA < 4 V)
• VDDSMB supply is removed. (VDDSMB < 2.35 V)
• Adapter – Battery voltage is less than V(DCINA-VFB) Comparator threshold
• Battery is over voltage
• In Thermal Shutdown: TSHUT IC temperature threshold is above 155°C

8.3.3 Automatic Internal Soft-Start Charger Current

The charger automatically soft-starts the output regulation current every time the charger is enabled to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists of stepping-up the charge regulation current into 8 evenly divided steps up to the programmed charge current. Each step lasts around 1.6 ms, for a typical rise time of 10ms. No external components are needed for this function. The regulation limits can be changed in the middle of charging without soft start.

8.3.4 Switching Frequency

The bq24765 switching frequency is 700 kHz. A high switching frequency allows a smaller inductor to give the same ripple current, or can be used to reduce the ripple current for the same inductor. A smaller inductor value may allow using a smaller inductor physical size, for a smaller board footprint area.

• Shaded areas are the most likely applications.
• External compensation can be recalculated if need other values.
• Lower current applications can use the inductance used at higher currents, but would operate in DCM more often.

8.3.5 Converter Operation

The synchronous buck PWM converter uses a fixed frequency (700 kHz) voltage mode with feed-forward control scheme. A type III compensation network allows using ceramic capacitors at the output of the converter. The compensation input stage is connected between the feedback output (FBO) and the error amplifier input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error amplifier output (EAO). The LC output filter selected gives a characteristic resonant frequency that is used to determine the compensation to ensure there is sufficient phase margin for the target bandwidth.

The resonant frequency, f_o, is given by:

An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the converter. The ramp height is one-fifteenth of the input adapter voltage making it always directly proportional to the input adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and simplifies the loop compensation. The ramp is offset by 200 mV in order to allow zero percent duty-cycle, when the EAO signal is below the ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order to get a 100% duty-cycle PWM request. Internal gate drive logic allows achieving 99.98% duty-cycle while ensuring the N-channel upper device always has enough voltage to stay fully on. If the BOOT pin to PHASE pin voltage falls below 4 V for more than 3 cycles, then the high-side n-channel power MOSFET is turned off and the low-side n-channel power MOSFET is turned on to pull the PHASE node down and recharge the BOOT capacitor. Then the high-side driver returns to 100% duty-cycle operation until the (BOOT-PHASE) voltage is detected to fall low again due to leakage current discharging the BOOT capacitor below the 4 V, and the recharge pulse is reissued.

The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible noise region. The type III compensation provides phase boost near the cross-over frequency, giving sufficient phase margin.

8.3.6 Refresh BTST Capacitor

If the BOOT pin to PHASE pin voltage falls below 4 V for more than 3 cycles, then the high-side n-channel power MOSFET is turned off and the low-side n-channel power MOSFET is turned on for 40ns to pull the PHASE node down and recharge the BOOT capacitor. The 40ns low-side MOSFET on-time is required protect from ringing noise, and to ensure the bootstrap capacitor is always recharged and able to keep the high-side power MOSFET on during the next cycle.

8.3.7 UCP (Charge Undercurrent): Using Sense Resistor

In bq24765, the cycle-by-cycle UCP allows using very small inductors seamlessly, even if they have large ripple current. Every cycle when the low-side MOSFET turns-on, if the CSOP-CSON voltage falls below 10 mV (inductor current falls below 1 A if using 10-mΩ sense resistor), the low-side MOSFET is latched off until the next cycle begins and resets the latch.

The converter automatically detects when to turn-off the low-side MOSFET every cycle. The inductor current ripple is given by

Equation 1.

where

• V_IN: adapter voltage
• V_VFB: Output Voltage = VFB voltage
• f_S: switching frequency = 700 kHz
• L_OUT: output inductor

For proper cycle-by-cycle UCP sensing, the output filter capacitor should sit on CSON. Only 0.1µF capacitor is on CSOP, close to the device input.

8.3.8 Cycle-By-Cycle Charge Overcurrent Protection, Using High-Side Sense-FET

The charger has a cycle-to-cycle over-current protection to protect from exceeding the maximum current capability of the integrated power MOSFETs. It monitors the drain current of the high-side power MOSFET using a sense-FET, and prevents the current from exceeding 10 A peak. The integrated high-side power MOSFET turns off when the over-current is detected, and latches off until the following cycle.

8.3.9 Average Charge Overcurrent Protection, Using Sense Resistor

The charger has an average over-current protection using the V(CSON-CSOP) voltage across the charge current sense resistor. It monitors the charge current, and prevents the current from exceeding 145% of programmed regulated charge current. If the charge current limit falls below 3.3 A (on 10 mΩ), the over current limit is fixed at 5 A. The high-side gate drive turns off when the over-current is detected, and automatically resumes when the current falls below the over-current threshold. There is an internal 160-kHz filter pole, to filter the switching frequency and prevent false tripping. This will add a small delay depending on the amount of overdrive over the threshold.

8.3.10 Battery Overvoltage Protection, Using Remote Sensing VFB

The converter will not allow switching when the battery voltage at VFB exceeds 104% of the regulation voltage set-point. Once the VFB voltage returns below 102% of the regulation voltage, switching resumes. This allows quick response to an over-voltage condition – such as occurs when the load is removed or the battery is disconnected. A 10-mA current sink from CSOP and CSON to AGND is on only during charging and allows discharging the stored output inductor energy that is transferred to the output capacitors.

8.3.11 Battery Short Protection

The bq24765 has a BAT LOWV comparator monitoring the output battery VFB voltage. If the voltage falls below 3.6 V, the battery short status is detected. Once the short status is detected, charger immediately stops for 2 ms to avoid inductor peak current surge. After 2 ms, the charger will soft-start again. If the battery voltage is still below 2.5 V, a 220-mA trickle charge current is applied. Otherwise, the charge current limit is set by ChargeCurrent(). Refer to Electrical Characteristics.

8.3.12 Battery Trickle Charging

The bq24765 automatically reduces the charge current limit to a fixed 220 mA to trickle charge the battery, when the voltage on the VFB pin falls below 2.5 V. The charge current returns to the value programmed on the ChargeCurrent(0x14) register, when the VFB pin voltage rises above 2.7 V. This function provides a safe trickle charge to close deeply discharged open packs.

8.3.13 High Accuracy VICM Using Current Sense Amplifier (CSA)

An industry standard, high accuracy current sense amplifier (CSA) is used to monitor the input current by the host or some discrete logic through the analog voltage output of the VICM pin. The CSA amplifies the input sensed voltage of CSSP-CSSN by 20x through the VICM pin. Once DCIN is above 4.5 V and ACIN is above 0.6 V, VICM no longer stays at ground, but becomes active. If the user wants to lower the voltage, they could use a resistor divider from VICM to AGND, and still achieve accuracy over temperature as the resistors can be matched their thermal coefficients.

A 100pF capacitor connected on the output is recommended for decoupling high-frequency noise.

8.3.14 VDDSMB Input Supply

The VDDSMB input provides bias power to the SMBus interface logic. Connect VDDSMB to an external 3.3-V or 5-V supply rail. SMBus communication can occur between host and charger when VDDSMB voltage above 2.5 V and VREF voltage at 3.3 V. Bypass VDDSMB to AGND with a 0.1-µF or greater ceramic capacitor.

8.3.15 Input Undervoltage Lockout (UVLO)

The system must have a minimum 4.5 V DCINA voltage to allow proper operation. When the DCINA voltage is below 4 V, VREF LDO stays inactive, even with ACIN above 0.6 V. VREF turns-on When DCINA>4.5 V and ACIN>0.6 V. To enable VDDP requires DCINA>4.5 V, ACIN>2.4 V and CE=HIGH.

8.3.16 VDDP Gate Drive Regulator

An integrated low-dropout (LDO) linear regulator provides a 6 V supply derived from DCINP, for high efficiency, and delivers over 90 mA of load current. The LDO powers the gate drivers of the n-channel switching MOSFETs. Bypass VDDP to PGND with a 1-µF or greater ceramic capacitor. During thermal shut down, VDDP LDO is disabled.

8.3.17 Input Current Comparator Trip Detection

In order to optimize the system performance, the host keeps an eye on the adapter current. Once the adapter current is above a threshold set via ICREF, the ICOUT pin sends signal to the HOST. The signal alarms the host that input power has exceeded the programmed limit, allowing the host to throttle back system power by reducing clock frequency, lowering rail voltages, or disabling certain parts of the system. The ICOUT pin is an open-drain output. Connect a pull-up resistor to ICOUT. The output is logic HI when the VICM output voltage (VICM = 20 x V(CSSP-CSSN)) is lower than the ICREF input voltage. The ICREF threshold is set by an external resistor divider using VREF. A hysteresis can be programmed by a positive feedback resistor from ICOUT pin to the ICREF pin.

Figure 13. ACOK, ICREF, and ICOUT Logic

8.3.18 Open-Drain Status Outputs (ACOK, ICOUT Pins)

Two status outputs are available, and they both require external pull up resistors to pull the pins to system digital rail for a high level. ACOK open-drain output goes high when ACIN is above 2.4 V. It indicates a good adapter is connected because of valid input voltage. ICOUT open-drain output goes low when the input current is higher than the programmed threshold via ICREF pin. Hysteresis can be programmed by putting a resistor from ICREF pin to ICOUT pin.

8.3.19 Thermal Shutdown Protection

The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off and self-protects whenever the junction temperature exceeds the TSHUT threshold of 155°C. VDDP LDO is disabled as well during thermal shut down. The charger stays off until the junction temperature falls below 135°C. Once the temperature drops below 135°C, VDDP LDO is enabled. If all the conditions described in “Enable and Disable Charging” section are valid, charge will soft start again.

8.3.20 Charger Timeout

The bq24765 includes a timer to terminate charging if the charger does not receive a ChargeVoltage() or ChargeCurrent() command within 170s. If a timeout occurs, both ChargeVoltage() and ChargeCurrent() commands must be resent to re-enable charging.

8.3.21 Charge Termination For Li-Ion or Li-Polymer

The primary termination method for Li-Ion and Li-Polymer is minimum current. Secondary temperature termination (see Electrical Characteristics) also provides additional safety. The host controls the charge initiation and the termination. A battery pack gas gauge assists the hosts on setting the voltages and determining when to terminate based on the battery pack state of charge.

8.3.22 Remote Sense

The bq24765 has a dedicated remote sense pin, VFB, which allows the rejection of board resistance and selector resistance. To fully utilize remote sensing, connect VFB directly to the battery interface through an unshared battery sense Kelvin trace, and place a 0.1-µF ceramic capacitor near the VFB pin to AGND.

Remote Kelvin Sensing provides higher regulation accuracy, by eliminating parasitic voltage drops. Remote sensing cancels the effect of impedance in series with the battery. This impedance normally causes the battery charger to prematurely enter constant-voltage mode with reducing charge current.

8.4.1 Continuous Conduction Mode and Discontinuous Conduction Mode

In Continuous Conduction Mode (CCM), the inductor current always flows to charge battery, and the charger always operates in synchronized mode. At the beginning of each clock cycle, high-side n-channel power MOSFET turns on, and the turn-on time is set by the voltage on the EAO pin. After the high-side power MOSFET turns off, the low-side n-channel power MOSFET turns on. During CCM, the low-side n-channel power MOSFET stays on until the end of the clock cycle. The internal gate drive logic ensures there is break-before-make switching to prevent shoot-through currents. During the 25 ns dead time where both FETs are off, the back-diode of the low-side power MOSFET conducts the inductor current. Having the low-side FET turn-on keeps the power dissipation low, and allows safely charging at high currents. With type III compensation, the loop has a fixed 2-pole system.

As the ripple valley current gets close to zero, charger operation goes to non-synchronized mode. During non-synchronous operation, after the high-side n-channel power MOSFET turns off, and after the break-before-make dead-time, the low-side n-channel power MOSFET will turn-on 40 ns. After the 40 ns blank out time is over, if V(CSOP-CSON) voltage falls below UCP threshold (typical 10 mV), the low-side power MOSFET will turn-off and stay off until the beginning of the next cycle, where the high-side power MOSFET is turned on again. After the low-side MOSFET turns off, the inductor current flows through back-gate diode until it reaches zero. The negative inductor current is blocked by the diode, and the inductor current will become discontinuous. This mode is called Discontinuous Conduction Mode (DCM).

During the DCM mode the loop response automatically changes and has a single pole system at which the pole is proportional to the load current, because the converter does not sink current, and only the load provides a current sink. This means at very low currents the loop response is slower, as there is less sinking current available to discharge the output voltage. At very low currents during non-synchronous operation, there may be a small amount of negative inductor current during the 40 ns recharge pulse. The charge should be low enough to be absorbed by the input capacitance.

Whenever the converter goes into zero percent duty-cycle, the high-side MOSFET does not turn on, and the low-side MOSFET does not turn on (no 40 ns recharge pulse) either, and there is no discharge from the battery; unless the BOOT to PHASE voltage discharges below 4 V. In that case, it pulses once to recharge the boot-strap capacitor.

8.5.1 Battery-Charger Commands

The bq24765 supports five battery-charger commands that use either Write-Word or Read-Word protocols, as summarized in Table 2. ManufacturerID() and DeviceID() can be used to identify the bq24765. On the bq24765, the ManufacturerID() command always returns 0x0040 and the DeviceID() command always returns 0x0006.

8.5.1.1 SMBus Interface

The bq24765 operates as a slave, receiving control inputs from the embedded controller host through the SMBus interface.

The bq24765 receives control inputs from the SMBus interface. The bq24765 uses a simplified subset of the commands documented in System Management Bus Specification V1.1, which can be downloaded from www.smbus.org. The bq24765 uses the SMBus Read-Word and Write-Word protocols (see Figure 14) to communicate with the smart battery. The bq24765 performs only as an SMBus slave device with address 0b0001001_ (0x12) and does not initiate communication on the bus. In addition, the bq24765 has two identification (ID) registers (0xFE): a 16-bit device ID register and a 16-bit manufacturer ID register (0xFF).

The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose pullup resistors (10 kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications.

Communication starts when the master signals a START condition, which is a high-to-low transition on SDA, while SCL is high. When the master has finished communicating, the master issues a STOP condition, which is a low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 15 and Figure 16 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and data bytes are transmitted between the START and STOP conditions. The SDA state changes only while SCL is low, except for the START and STOP conditions. Data is transmitted in 8-bit bytes and is sampled on the rising edge of SCL. Nine clock cycles are required to transfer each byte in or out of the bq24765 because either the master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle.

Figure 14. SMBus Write-Word and Read-Word Protocols

Figure 15. SMBus Write Timing

Figure 16. SMBus Read Timing

8.5.2 Battery Voltage Regulation

The bq24765 uses a high-accuracy voltage regulator for charging voltage. The battery voltage regulation setting is programmed by the host microcontroller (µC), through the SMBus interface that sets an 11 bit DAC. The battery termination voltage is function of the battery chemistry. Consult the battery manufacturer to determine this voltage.

The VFB pin is used to sense the battery voltage for voltage regulation and should be connected as close to the battery as possible, or directly on the output capacitor. A 0.1-µF ceramic capacitor from VFB to AGND is recommended to be as close to the VFB pin as possible to decouple high frequency noise.

To set the output charge voltage regulation limit, use the SMBus to write a 16 bit ChargeVoltage() command using the data format listed in Table 3. The ChargeVoltage() command uses the Write-Word protocol (see Figure 14). The command code for ChargeVoltage() is 0x15 (0b00010101). The bq24765 provides a 1.024-V to 19.200-V charge voltage range, with 16 mV resolution. Setting ChargeVoltage() below 1.024 V or above 19.2 V clears DAC, and terminates charge.

Upon reset, the ChargeVoltage() and ChargeCurrent() values are cleared (0) and the charger remains off until both the ChargeVoltage() and the ChargeCurrent() command are sent. During reset, both high side and low side fets remain off until the charger gets started.

8.5.3 Battery Current Regulation

The Charge Current SMBus 6 bit DAC register sets the maximum charging current. Battery current is sensed by resistor RSR connected between CSOP and CSON. The maximum full-scale differential voltage between CSOP and CSON is 80.64 mV. Thus, for a 0.010-Ω sense resistor, the maximum charging current is 8.064 A.

The CSOP and CSON pins are used to sense across RSR with default value of 10 mΩ. However, resistors of other values can also be used. For a larger the sense resistor, you get a larger sense voltage, and a higher regulation accuracy; but, at the expense of higher conduction loss.

To set the charge current, use the SMBus to write a 16bit ChargeCurrent() command using the data format listed in Table 4. The ChargeCurrent() command uses the Write-Word protocol (see Figure 14). The command code for ChargeCurrent() is 0x14 (0b00010100). When using a 10-mΩ sense resistor, the bq24765 provides a charge current range of 128 mA to 8.064 A, with 128 mA resolution. Set ChargeCurrent() to 0 to terminate charging. Setting ChargeCurrent() below 128 mA, or above 8.064 A clears DAC and terminates charge

As charging goes on, the power loss on the switching fets causes the junction temperature to rise. The bq24765 provides a thermal regulation loop to throttle back the maximum charge current when the maximum junction temperature limit is reached. Once the device junction temperature exceeds thermal regulation limit (typical 120°C), the thermal regulator reduces the charging current to keep the junction temperature at 120°C. When the junction temperature rises to 125°C, the charging current decreases down close to 0 A.

The bq24765 includes a foldback current limit when the battery voltage is low. If the battery voltage is less than 3.6 V but above 2.5 V, any charge current limit above 3 A will be clamped at 3 A. If the battery voltage is less than 2.5 V, the charge current is set to 220 mA until that voltage rises above 2.7 V. The ChargeCurrent() register is preserved and becomes active again when the battery voltage is higher than 2.7 V. This function effectively provides a fold-back current limit, which protects the charger during short circuit and overload.

Upon reset, the ChargeVoltage() and ChargeCurrent() values are cleared (0) and the charger remains off until both the ChargeVoltage() and the ChargeCurrent() command are sent. During reset, both high side and low side fets remain off until the charger gets started.

8.5.4 Input Adapter Current Regulation

The total Input Current from an AC adapter or other DC sources is a function of the system supply current and the battery charging current. System current normally fluctuates as portions of the system are powered up or down. Without Dynamic Power Management (DPM), the source must be able to supply the maximum system current and the maximum charger input current simultaneously. By using DPM, the input current regulator reduces the charging current to keep the input current from exceeding the limit set by the Input Current SMBus 6 bit DAC register. With the high accuracy limiting, the current capability of the AC adaptor can be lowered, reducing system cost.

The CSSP and CSSN pins are used to sense R_AC with default value of 10 mΩ. However, resistors of other values can also be used. For a larger the sense resistor, you get a larger sense voltage, and a higher regulation accuracy; but, at the expense of higher conduction loss.

The total input current, from a wall cube or other DC source, is the sum of the system supply current and the current required by the charger. When the input current exceeds the set input current limit, the bq24765 decreases the charge current to provide priority to system load current. As the system supply rises, the available charge current drops linearly to zero.

where η is the efficiency of the DC-DC converter (typically 85% to 95%).

Equation 2.

To set the input current limit, use the SMBus to write a 16-bit InputCurrent() command using the data format listed in Table 5. The InputCurrent() command uses the Write-Word protocol (see Figure 14). The command code for InputCurrent() is 0x3F (0b00111111). When using a 10-mΩ sense resistor, the bq24765 provides an input-current limit range of 256 mA to 11.004 A, with 256 mA resolution. InputCurrent() settings from 1 mA to 256 mA clears DAC and terminates charge. Upon reset the input current limit is 256 mA.

Table 3. Charge Voltage Register (0x15)

Table 4. Charge Current Register (0x14), Using 10-mω Sense Resistor

Table 5. Input Current Register (0x3f), Using 10-mω Sense Resistor