SLUS999A November   2009  – November 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SMB Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adapter Detect and Power Up
      2. 8.3.2  Enable and Disable Charging
      3. 8.3.3  Automatic Internal Soft-Start Charger Current
      4. 8.3.4  Switching Frequency
      5. 8.3.5  Converter Operation
      6. 8.3.6  Refresh BTST Capacitor
      7. 8.3.7  UCP (Charge Undercurrent): Using Sense Resistor
      8. 8.3.8  Cycle-By-Cycle Charge Overcurrent Protection, Using High-Side Sense-FET
      9. 8.3.9  Average Charge Overcurrent Protection, Using Sense Resistor
      10. 8.3.10 Battery Overvoltage Protection, Using Remote Sensing VFB
      11. 8.3.11 Battery Short Protection
      12. 8.3.12 Battery Trickle Charging
      13. 8.3.13 High Accuracy VICM Using Current Sense Amplifier (CSA)
      14. 8.3.14 VDDSMB Input Supply
      15. 8.3.15 Input Undervoltage Lockout (UVLO)
      16. 8.3.16 VDDP Gate Drive Regulator
      17. 8.3.17 Input Current Comparator Trip Detection
      18. 8.3.18 Open-Drain Status Outputs (ACOK, ICOUT Pins)
      19. 8.3.19 Thermal Shutdown Protection
      20. 8.3.20 Charger Timeout
      21. 8.3.21 Charge Termination For Li-Ion or Li-Polymer
      22. 8.3.22 Remote Sense
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Conduction Mode and Discontinuous Conduction Mode
    5. 8.5 Programming
      1. 8.5.1 Battery-Charger Commands
        1. 8.5.1.1 SMBus Interface
      2. 8.5.2 Battery Voltage Regulation
      3. 8.5.3 Battery Current Regulation
      4. 8.5.4 Input Adapter Current Regulation
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

RUV Package
34-Pin VQFN
Top View
bq24765 po8_lus999.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
ACIN 9 I Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from adapter input to ACIN pin to AGND pin. ACOK open-drain output is pulled high and charge is allowed when ACIN pin voltage is greater than 2.4V. VREF regulator and VICM current sense amplifier are active when ACIN pin voltage is greater than 0.6V, and DCINA>VDCIN_UVLO.
ACOK 18 O Valid adapter active-high detect logic open-drain output. Pulled HI when Input voltage is above ACIN programmed threshold and DCINA is above UVLO threshold. Connect a 10-kΩ pull-up resistor from ACOK pin to pull-up supply rail.
AGND 19 AGND Analog Ground. On PCB layout, connect to the analog ground plane, and only connect to PGND through the power-pad underneath the IC.
BOOT 26 P PWM high side driver positive supply. Connect a 0.1uF bootstrap ceramic capacitor from BOOT to PHASE. Connect a small bootstrap Schottky diode from VDDP to BOOT.
CE 13 I Charge enable active-high logic input. HI enables charge. LO disables charge. Pull up CE using 10kOhm resistor or connect directly to VREF to enable charger.
CSON 21 P Charge current sense resistor, negative input. An optional 0.1-uF ceramic capacitor is placed from CSON pin to AGND for common-mode filtering. A 0.1-uF ceramic capacitor is placed from CSON to CSOP to provide differential-mode filtering. The capacitor of the output LC filter is placed on CSON.
CSOP 22 P Charge current sense resistor, positive input. A 0.1-uF ceramic capacitor is placed from CSOP pin to AGND for common mode filtering. A 0.1-uF ceramic capacitor is placed from CSON to CSOP to provide differential-mode filtering.
CSSN 5 P Adapter current sense resistor, negative input. An optional 0.1-uF ceramic capacitor is placed from CSSN pin to AGND for common-mode filtering. A 0.1-uF ceramic capacitor is placed from CSSN to CSSP to provide differential-mode filtering.
CSSP 6 P Adapter current sense resistor, positive input. A 0.1-uF ceramic capacitor is placed from CSSP pin to AGND for common-mode filtering. A 0.1-uF ceramic capacitor is placed from CSSN to CSSP to provide differential-mode filtering.
DCINA 25 P Analog sense of IC power positive supply for internal reference bias circuit. Connect directly to adapter input, or to diode-OR point of adapter and battery. Place a 20Ω and 0.5uF ceramic capacitor filter from adapter to AGND pin close to the IC and connect to DCINA on the node between the resistor and capacitor.
DCINP 2 P High current input for IC power positive supply, and connection to drain of high-side power MOSFET. Place two 10uF ceramic capacitors from DCINP to PGND pin close to the IC.
DCINP 3 P High current input for IC power positive supply, and connection to drain of high-side power MOSFET. Place two 10uF ceramic capacitors from DCINP to PGND pin close to the IC.
DCINP 4 P High current input for IC power positive supply, and connection to drain of high-side power MOSFET. Place two 10uF ceramic capacitors from DCINP to PGND pin close to the IC.
EAI 11 I Error Amplifier Input for compensation. Connect the feedback compensation components from EAI to EAO. Connect the input compensation from FBO to EAI.
EAO 10 I Error Amplifier Output for compensation. Connect the feedback compensation components from EAO to EAI. Typically, a capacitor in parallel with a series resistor and capacitor. This node is internally compared to the PWM saw-tooth oscillator signal.
FBO 12 O Feedback Output for compensation. Connect the input compensation from FBO to EAI. Typically, a resistor in parallel with a series resistor and capacitor.
ICOUT 23 O Low power mode detect active-high open-drain logic output. Place a 10kohm pull-up resistor from ICOUT pin to the pull-up voltage rail. Place a positive feedback resistor from ICOUT pin to ICREF pin for programming hysteresis. The output is HI when VICM pin voltage is lower than ICREF pin voltage. The output is LO when VICM pin voltage is higher than ICREF pin voltage.
ICREF 8 I Low power voltage set input. Connect a resistor divider from VREF to ICREF, and AGND to program the reference for the LOPWR comparator. The ICREF pin voltage is compared to the VICM pin voltage and the logic output is given on the ICOUT open-drain pin. Connecting a positive feedback resistor from ICREF pin to ICOUT pin programs the hysteresis.
PGND 1 PGND Power ground. Connection to source of integrated low-side power MOSFET. On PCB layout, connect to ground connection of input and output capacitors of the charger. Only connect to AGND through the power-pad underneath the IC.
PGND 32 PGND Power ground. Connection to source of integrated low-side power MOSFET. On PCB layout, connect to ground connection of in put and out put capacitors of the charger. Only connect to AGND through the power-pad underneath the IC.
PGND 33 PGND Power ground. Connection to source of integrated low-side power MOSFET. On PCB layout, connect to ground connection of in put and out put capacitors of the charger. Only connect to AGND through the power-pad underneath the IC
PGND 34 PGND Power ground. Connection to source of integrated low-side power MOSFET. On PCB layout, connect to ground connection of in put and out put capacitors of the charger. Only connect to AGND through the power-pad underneath the IC.
PHASE 28 P Phase switching node (junction of the integrated high-side power MOSFET source and the integrated low-side power MOSFET drain). Connect to the output inductor. Connect the 0.1uF bootstrap ceramic capacitor from PHASE to BOOT
PHASE 27 P Phase switching node (junction of the integrated high-side power MOSFET source and the integrated low-side power MOSFET drain). Connect to the output inductor. Connect the 0.1uF bootstrap ceramic capacitor from PHASE to BOOT.
PHASE 29 P Phase switching node (junction of the integrated high-side power MOSFET source and the integrated low-side power MOSFET drain). Connect to the output inductor. Connect the 0.1uF bootstrap ceramic capacitor from PHASE to BOOT
PHASE 30 P Phase switching node (junction of the integrated high-side power MOSFET source and the integrated low-side power MOSFET drain). Connect to the output inductor. Connect the 0.1uF bootstrap ceramic capacitor from PHASE to BOOT.
PHASE 31 P Phase switching node (junction of the integrated high-side power MOSFET source and the integrated low-side power MOSFET drain). Connect to the output inductor. Connect the 0.1uF bootstrap ceramic capacitor from PHASE to BOOT.
SCL 16 I SMBus Clock input. Connect to SMBus clock line from the host controller. A 10-kohm pull-up resistor to the host controller power rail is needed.
SDA 15 I SMBus Data input. Connect to SMBus data line from the host controller. A 10-kohm pull-up resistor to the host controller power rail is needed.
VDDP 24 P PWM low side driver positive 6V supply output. Connect a 1uF ceramic capacitor from VDDP to PGND pin, close to the IC. Use for high-side driver bootstrap voltage by connecting a small signal Schottky diode from VDDP to BOOT.
VDDSMB 17 I Input voltage for SMBus logic. Connect a 3.3V always supply rail, or 5V always rail to VDDSMB pin. Connect a 0.1uF ceramic capacitor from VDDSMB to AGND for decoupling.
VFB 20 I Battery voltage remote sense. Directly connect a Kelvin sense trace from the battery pack positive terminal to the VFB pin to accurately sense the battery pack voltage. Place a 0.1-uF capacitor from VFB to AGND close to the IC to filter high frequency noise.
VICM 14 O Adapter current sense amplifier output. VICM voltage is 20 times the differential voltage across CSSP-CSSN. Place a 100pF (max) or less ceramic decoupling capacitor from VICM to AGND.
VREF 7 P 3.3V regulated voltage output. Place a 1uF ceramic capacitor from VREF to AGND pin close to the IC. This voltage could be used for programming the ICREF threshold. VREF can directly connect to VDDSMB as SMBus supply, or serve as pull up supply rail for CE, ACOK and ICOUT.
Power Pad GND Exposed pad beneath the IC. AGND and PGND star-connected only at the Power Pad plane. Always solder Power Pad to the board, and have vias on the Power Pad plane connecting to AGND and PGND planes. It also serves as a thermal pad to dissipate heat.