SLUSC27C April   2015  – March 2017

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Power Up
        1. 7.3.1.1 Battery Only
        2. 7.3.1.2 Adapter Detect and ACOK Output
          1. 7.3.1.2.1 Adapter Overvoltage (ACOVP)
      2. 7.3.2 System Power Selection
      3. 7.3.3 Enable and Disable Charging
        1. 7.3.3.1 Automatic Internal Soft-Start Charger Current
      4. 7.3.4 Current and Power Monitor
        1. 7.3.4.1 High Accuracy Current Sense Amplifier (IADP and IDCHG)
        2. 7.3.4.2 High Accuracy Power Sense Amplifier (PMON)
      5. 7.3.5 Processor Hot Indication for CPU Throttling
      6. 7.3.6 Converter Operation
        1. 7.3.6.1 Continuous Conduction Mode (CCM)
        2. 7.3.6.2 Discontinuous Conduction Mode (DCM)
        3. 7.3.6.3 Non-Sync Mode and Light Load Comparator
        4. 7.3.6.4 EMI Switching Frequency Adjust
      7. 7.3.7 Battery LEARN Cycle
      8. 7.3.8 Charger Timeout
      9. 7.3.9 Device Protections Features
        1. 7.3.9.1 Input Overcurrent Protection (ACOC)
        2. 7.3.9.2 Charge Overcurrent Protection (CHGOCP)
        3. 7.3.9.3 Battery Overvoltage Protection (BATOVP)
        4. 7.3.9.4 Battery Short
        5. 7.3.9.5 Thermal Shutdown Protection (TSHUT)
        6. 7.3.9.6 Inductor Short, MOSFET Short Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Battery Charging
      2. 7.4.2 Hybrid Power Boost Mode
        1. 7.4.2.1 Battery Discharge Current Regulation in Hybrid Power Boost Mode
    5. 7.5 Programming
      1. 7.5.1 SMBus Interface
        1. 7.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 7.5.1.2 Timing Diagrams
    6. 7.6 Register Maps
      1. 7.6.1  Battery-Charger Commands
      2. 7.6.2  Setting Charger Options
        1. 7.6.2.1 ChargeOption0 Register
      3. 7.6.3  ChargeOption1 Register
      4. 7.6.4  ChargeOption2 Register
      5. 7.6.5  ChargeOption3 Register
      6. 7.6.6  ProchotOption0 Register
      7. 7.6.7  ProchotOption1 Register
      8. 7.6.8  ProchotStatus Register
      9. 7.6.9  Setting the Charge Current
      10. 7.6.10 Setting the Charge Voltage
      11. 7.6.11 Setting Input Current
      12. 7.6.12 Setting the Discharge Current
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Negative Output Voltage Protection
        2. 8.2.2.2 Reverse Input Voltage Protection
        3. 8.2.2.3 Reduce Battery Quiescent Current
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Input Capacitor
        6. 8.2.2.6 Output Capacitor
        7. 8.2.2.7 Power MOSFETs Selection
        8. 8.2.2.8 Input Filter Design
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 Layout Consideration of Current Path
      2. 10.2.2 Layout Consideration of Short Circuit Protection
      3. 10.2.3 Layout Consideration for Short Circuit Protection
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loop (see Figure 33) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB according to this specific order is essential.

  1. Place input capacitor as close as possible to switching MOSFET’s supply and ground connections and use shortest copper trace connection. These parts should be placed on the same layer of PCB instead of on different layers and using vias to make this connection.
  2. The IC should be placed close to the switching MOSFET’s gate pins and keep the gate drive signal traces short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of switching MOSFETs.
  3. Place inductor input pin to switching MOSFET’s output pin as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane.
  4. The charging current sensing resistor should be placed right next to the inductor output. Route the sense leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop area) and do not route the sense leads through a high-current path (see Figure 34 for Kelvin connection for best current accuracy). Place decoupling capacitor on these traces next to the IC
  5. Place output capacitor next to the sensing resistor output and ground
  6. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor ground before connecting to system ground.
  7. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC use analog ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling
  8. Route analog ground separately from power ground. Connect analog ground and connect power ground separately. Connect analog ground and power ground together using power pad as the single ground connection point. Or using a 0Ω resistor to tie analog ground to power ground (power pad should tie to analog ground in this case if possible).
  9. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible
  10. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers.
  11. The via size and number should be enough for a given current path.

See the EVM design for the recommended component placement with trace and via locations. For the WQFN information, See SCBA017 and SLUA271.

10.2 Layout Examples

10.2.1 Layout Consideration of Current Path

bq24780S hi_f_path_lusa79.gif Figure 33. High Frequency Current Path

10.2.2 Layout Consideration of Short Circuit Protection

bq24780S sens_res_layout_lusa79.gif Figure 34. Sensing Resistor PCB Layout

10.2.3 Layout Consideration for Short Circuit Protection

The bq24780S has a unique short circuit protection feature. Its cycle-by-cycle current monitoring feature is achieved through monitoring the voltage drop across RDS(on) of the MOSFETs after a certain amount of blanking time. For a MOSFET short or inductor short circuit, the over current condition is sensed by two comparators, and two counters are triggered. After seven occurrences of a short circuit event, the charger will be latched off. To reset the charger from latch-off status, reconnect the adapter. Figure 35 shows the bq24780S short circuit protection block diagram.

bq24780S shrt_cir_bd_lusbw0.gif Figure 35. Block Diagram of bq24780S Short Circuit Protection

In normal operation, the low side MOSFET current is from source to drain which generates a negative voltage drop when it turns on, as a result the over current comparator can not be triggered. When the high side switch short circuit or inductor short circuit happens, the large current of low side MOSFET is from drain to source and can trigger low side switch over current comparator. The bq24780S senses the low side switch voltage drop through the PHASE pin and GND pin.

The high-side FET short is detected by monitoring the voltage drop between ACP and PHASE. As a result, it not only monitors the high side switch voltage drop, but also the adapter sensing resistor voltage drop and PCB trace voltage drop from ACN pin of RAC to charger high side switch drain. Usually, there is a long trance between input sensing resistor and charger converting input, a careful layout will minimize the trace effect.

To prevent unintentional charger shut down in normal operation, MOSFET RDS(on) selection and PCB layout is very important. Figure 36 shows a improvement PCB layout example and its equivalent circuit. In this layout, the system current path and charger input current path is not separated, as a result, the system current causes voltage drop in the PCB copper and is sensed by the IC. The worst layout is when a system current pull point is after charger input; as a result all system current voltage drops are counted into over current protection comparator. The worst case for IC is when the total system current and charger input current sum equals the DPM current. When the system pulls more current, the charger IC tries to regulate the RAC current as a constant current by reducing the charging current.

bq24780S PCB_layout_lusbw0.gif Figure 36. PCB Layout Example

Figure 37 shows the optimized PCB layout example. The system current path and charge input current path is separated, as a result the IC only senses charger input current caused PCB voltage drop and minimized the possibility of unintentional charger shut down in normal operation. This also makes PCB layout easier for high system current application.

bq24780S opti_PCB_lusbw0.gif Figure 37. Optimized PCB Layout Example

The total voltage drop sensed by IC can be express as the following equation.

Equation 17. Vtop = RAC x IDPM + RPCB x (ICHRGIN + (IDPM - ICHRGIN) x k) + RDS(on) x IPEAK

where the RAC is the AC adapter current sensing resistance, IDPM is the DPM current set point, RPCB is the PCB trace equivalent resistance, ICHRGIN is the charger input current, k is the PCB factor, RDS(on) is the high side MOSFET turn on resistance and IPEAK is the peak current of inductor. Here the PCB factor k equals 0 means the best layout shown in Figure 37 where the PCB trace only goes through charger input current while k equals 1 means the worst layout shown in Figure 36 where the PCB trace goes through all the DPM current. The total voltage drop must below the high side short circuit protection threshold to prevent unintentional charger shut down in normal operation.

The low side MOSFET short circuit voltage drop threshold can be adjusted via SMBus command. ChargeOption() bit[7] =0, 1 set the low side threshold 135mV and 230mV respectively. The high side MOSFET short circuit voltage drop threshold can be adjusted via SMBus command. ChargeOption() bit[8] = 0, 1 disable the function and set the threshold 750mV respectively. For a fixed PCB layout, host should set proper short circuit protection threshold level to prevent unintentional charger shut down in normal operation.