9.3.1 Ship Mode

Ship Mode is the lowest quiescent current state for the device. Ship Mode latches off the device and BAT FET until V_IN > V_UVLO or the MR button is depressed for t_WAKE1 and released. To enter Ship Mode, CD must be pulled high. If the EN_SHIPMODE is written to a 1 while the input is connected, it must first be removed to enter ship mode. This allows the end product with minimal load on the battery, and the end user can enable the device by plugging it into the adapter or by toggling the MR button. The battery voltage must be above the maximum programmable BUVLO threshold in order to exit Ship mode with a MR button press when V_IN is not present.. The EN_SHIPMODE bit can be cleared using the I²C interface as well while the input is valid. The following list shows the events that are active during Ship Mode:

1. VIN_UV Comparator
2. MR Input (No clock or delay in this mode for lowest power consumption)

9.3.2 High Impedance Mode

High Impedance mode is the lowest quiescent current state while operating from the battery. During Hi-Z mode the SYS output is powered by BAT, the MR input is active, and the LSCTRL input is active. All other circuits are in a low power or sleep state.The LS/LDO output can be enabled in Hi-Z mode with the LSCTRL input. If the LS/LDO output has been enabled through I²C prior to entering Hi-Z mode, it will stay enabled. The CD pin is used to put the device in a high-impedance mode when battery is present and V_IN < V_UVLO. Drive CD high to enable the device and enter active battery operation when V_IN is not valid. When the HZ_MODE bit is written by the host, the I²C interface is disabled if only battery is present. To resume I²C, the CD pin must be toggled. The functionality is shown in Table 1.

9.3.3 Active Battery Only Connected

When the battery above V_BATUVLO is connected with no input source, the battery discharge FET is turned on. After the battery rises above V_BATUVLO and the deglitch time is reached, the SYS output starts to rise. The current from PMID and SYS is not regulated, but is protected by a short circuit current limit. If the short circuit limit is reached for the deglitch time (t_{DGL_SC}), the battery discharge FET is turned off for the recovery time (t_{REC_SC}). After the recovery time, the battery FET is turned on to test if the short has been removed. If it has not, the FET turns off and the process repeats until the short is removed. This process protects the internal FET from over current. During this event PMID will likely droop and cause SYS to go out of regulation.

To provide designers the most flexibility in optimizing their system, an adjustable BATUVLO is provided. When the voltage drops below the V_BATUVLO threshold, the battery discharge FET is turned off. Deeper discharge of the battery enables longer times between charging, but may shorten the battery life. The BATUVLO is adjustable with a fixed 100-mV hysteresis.

If a valid V_IN is connected during active battery mode, V_IN > V_UVLO, the supplement and battery discharge FET is turned on when the battery voltage is above the minimum V_BATUVLO.

Drive CD high or write the CE register to disable charge when V_IN > V_UVLO is present. CD is internally pulled down. When exiting this mode, charging resumes if V_IN is present, CD is low and charging is enabled.

All HOST interfaces (CD, SDA/SCL, INT, RESET and LSCTRL) are active no later than 5 ms after SYS reaches the programmed level.

9.3.4 Voltage Based Battery Monitor

The device implements a simple voltage battery monitor which can be used to determine the depth of discharge. Prior to entering High-Z mode, the device will initiate a VBMON reading. The host can read the latched value for the no-load battery voltage, or initiate a reading using VBMON_READ to see the battery voltage under a known load. The register will be updated and can be read 2ms after a read is initiated. The VBMON voltage threshold is readable with 2% increments with ±1.5% accuracy between 60% and 100% of VBATREG using the VBMON_TH registers.  Reading the value during charge is possible, but for the most accurate battery voltage indication, it is recommended to disable charge, initiate a read, and then re-enable charge.

A typical discharge profile for a Li-Ion battery is shown in Table 2. The specific battery to be used in the application should be fully characterized to determine the thresholds that will indicate the appropriate battery status to the user. Two typical examples are shown below, assuming the VBMON reading is taken with no load on the battery.

This function enables a simple 5-bar status indicator with the following typical performance with different VBATREG settings:

Figure 15. Voltage Battery Monitor

9.3.5 Sleep Mode

The device enters the low-power sleep mode if the voltage IN falls below the sleep-mode entry threshold and V_IN is higher than the undervoltage lockout threshold. In sleep mode, the input is isolated from the battery. This feature prevents draining the battery during the absence of V_IN. When V_IN < V_(BAT) + V_SLP, the device turns the battery discharge FET on, sends a 128-µs pulse on the INT output, and the FAULT bits of the register are update over I²C. Once V_IN > V_(BAT) + V_SLP, the device initiates a new charge cycle. The FAULT bits are not cleared until they are read over I²C and the sleep condition no longer exists.

9.3.6 Input Voltage Based Dynamic Power Management (V_IN(DPM))

During the normal charging process, if the input power source is not able to support the programmed or default charging current and System load, the supply voltage decreases. Once the supply drops to V_IN(DPM), the input DPM current and voltage loops will reduce the input current through the blocking FETs, to prevent the further drop of the supply. The V_IN(DPM) threshold is programmable through the I²C register from 4.2 V to 4.9 V in 100-mV steps. It can be disabled completely as well. When the device enters this mode, the charge current may be lower than the set value and the VINDPM_STAT bit is set. If the 2X timer is set, the safety timer is extended while V_IN(DPM) is active. Additionally, termination is disabled.

9.3.7 Input Overvoltage Protection and Undervoltage Status Indication

The input overvoltage protection protects the device and downstream components connected to PMID, SYS, and BAT against damage from overvoltage on the input supply. When V_IN > V_OVP an OVP fault is determined to exist. During the OVP fault, the device turns the battery discharge FET on, sends a single 128-µs pulse on INT, and the FAULT bits are updated over I²C. Once the OVP fault is removed, after the deglitch time, t_{DGL_OVP}, STAT and FAULT bits are cleared and the device returns to normal operation. The FAULT bits are not cleared until they are read in from I²C after the OVP condition no longer exists. The OVP threshold for the device is set to operate from standard USB sources.

The input under-voltage status indication is used to notify the host or other device when the input voltage falls below a desired threshold. When V_IN < V_UVLO, after the deglitch time t_{DGL_UVLO}, a UVLO fault is determined to exist. During the V_IN UVLO fault, the device sends a single 128-µs pulse on INT, and the STAT and FAULT bits are updated over I²C. The FAULT bits are not cleared until they are read in from I²C after the UVLO condition no longer exists.

9.3.8 Battery Charging Process and Charge Profile

When a valid input source is connected (V_IN > V_UVLO and V_(BAT) + V_SLP < V_IN < V_OVP), the CE bit in the control register determines whether a charge cycle is initiated. When the CE bit is 1 and a valid input source is connected, the battery discharge FET is turned off, and the output at SYS is regulated depending on the output configuration. A charge cycle is initiated when the CE bit is written to a 0. Alternatively, the CD input can be used to enable and disable charge.

The device supports multiple battery chemistries for single-cell applications. Charging is done through the internal battery MOSFET. There are several loops that influence the charge current: constant current loop (CC), constant voltage loop (CV), input current limit, V_DPPM, and V_IN(DPM). During the charging process, all loops are enabled and the one that is dominant takes control.

The charge current is regulated to I_CHARGE until the voltage between BAT and GND reaches the regulation voltage. The voltage between BAT and GND is regulated to V_BATREG (CV Mode) while the charge current naturally tapers down. When termination is enabled, the device monitors the charging current during the CV mode, and once the charge current tapers down to the termination threshold, I_TERM, and the battery voltage is above the recharge threshold, the device terminates charge, and turns off the battery charging FET. Termination is disabled when any loop is active other than CV.

9.3.9 Dynamic Power Path Management Mode

With a valid input source connected, the power-path management circuitry monitors the input voltage and current continuously. The current into IN is shared at PMID between charging the battery and powering the system load at PMID, SYS, and LS/LDO. If the sum of the charging and load currents exceeds the preset maximum input current, the input DPM loop reduces input current. If PMID drops below the DPPM voltage threshold, the charging current is reduced by the DPPM loop through the BATFET. If PMID continues to drop after BATFET charging current is reduced to zero, the part enters supplement mode when PMID falls below the supplement mode threshold. Battery termination is disabled while in DPPM mode.

9.3.10 Battery Supplement Mode

While in DPPM mode, if the charging current falls to zero and the system load current increases beyond the programmed input current limit, the voltage at PMID reduces further. When the PMID voltage drops below the battery voltage by V_(BSUP1), the battery supplements the system load. The battery stops supplementing the system load when the voltage on the PMID pin rises above the battery voltage by V_(BSUP2). During supplement mode, the battery supplement current is not regulated, however, the short-circuit protection circuit is active. Battery termination is disabled while in supplement mode.

9.3.11 Default Mode

The default mode is used when there is no host, or I²C communication is not available. If the externally programmable pins, ILIM, ISET, and ITERM have resistors connected, that is considered the default mode. If they are tied to GND, the default register settings are used. The default mode can be entered by connecting a valid power source to V_IN or the RESET bit is written. Default mode is exited by writing to the I²C interface.

9.3.12 Termination and Pre-Charge Current Programming by External Components (IPRETERM)

The termination current threshold is user programmable through an external resistor or through registers over I²C. Set the termination current using the IPRETERM pin by connecting a resistor from IPRETERM to GND. The termination can be set between 5% and 20% of the programmed output current set by ISET, using Table 3 for guidance:

Using the I²C register, the termination current can be programmed with a minimum of 500 µA and a maximum of 37 mA.  

The pre-charge current is not independently programmable through the external resistor, and is set at the termination current. The pre-charge and termination currents are programmable using the IPRETERM registers. If no IPRETERM resistor is connected and the pin is tied to GND, the default values in the IPRETERM registers are used. The external value can be used in host mode by configuring the IPRETERM registers. If the external ICHG setting will be used after being in Host mode, the IPRETERM registers should be set to match the desired external threshold for the highest ICHG accuracy.

Termination is disabled when any loop other than CV is active.

9.3.13 Input Current Limit Programming by External Components (ILIM)

The input current limit threshold is user programmable through an external resistor or through registers over I²C. Set the input current limit using the ILIM pin by connecting a resistor from ILIM to GND using Table 4 for guidance. If no ILIM resistor is connected and the pin is tied to GND, the default ILIM register value is used. The external value is not valid once the device enters host mode.

The device has register programmable input current limits from 50 mA to 400 mA in 50-mA steps. The device is USB-IF compliant for inrush current testing, assuming that the input capacitance to the device is selected to be small enough to prevent a violation (<10 µF), as this current is not limited.

9.3.14 Charge Current Programming by External Components (ISET)

The fast charge current is user programmable through an external resistor or through registers over I²C. Set the fast charge current by connecting a resistor from ISET to GND. If no ISET resistor is connected and the pin is tied to GND, the default ISET register value is used. While charging, if the charge current is using the externally programmed value, the voltage at ISET reflects the actual charging current and can be used to monitor charge current. The current out of ISET is 1/100 (±10%) of the charge current. The charge current can be calculated by using Table 5 for guidance:

9.3.15 Safety Timer and Watchdog Timer

At the beginning of the charge cycle, the device starts the safety timer. If charging has not terminated before the programmed safety time, t_MAXCHG, expires, the device enters idle mode and charging is disabled. The pre-charge safety time, t_PRECHG, is 10% of t_MAXCHG. When a safety timer fault occurs, a single 128 µs pulse is sent on the INT pin and the STAT and FAULT bits of the status registers are updated over I²C. The CD pin or power must be toggled in order to clear the safety timer fault. The safety timer duration is programmable using the TMR bits. When the safety timer is active, changing the safety timer duration resets the safety timer. The device also contains a 2X_TIMER bit that enables the 2X timer function to prevent premature safety timer expiration when the charge current is reduced by a load on PMID, SYS, LS/LDO or a NTC condition. When t_{2X_TIMER} function is enabled, the timer is allowed to run at half speed when any loop is active other than CC or CV.

In addition to the safety timer, the device contains a 50-second watchdog timer that monitors the host through the I²C interface. Once any I²C transaction is performed on the I²C interface, a watchdog timer is started. The watchdog timer is reset by any transaction by the host using the I²C interface. If the watchdog timer expires without a reset from the I²C interface, all registers except MRRESET_VIN and MRREC are reset to the default values.

9.3.16 External NTC Monitoring (TS)

The I²C interface allows the user to easily implement the JEITA standard for systems where the battery pack thermistor is monitored by the host. Additionally, the device provides a flexible voltage based TS input for monitoring the battery pack NTC thermistor. The voltage at TS is monitored to determine that the battery is at a safe temperature during charging.

To satisfy the JEITA requirements, four temperature thresholds are monitored: the cold battery threshold, the cool battery threshold, the warm battery threshold, and the hot battery threshold. These temperatures correspond to the V_(COLD), V_(COOL), V_(WARM), and V_(HOT) threshold in the Electrical Characteristics. Charging and timers are suspended when V_(TS) < V_(HOT) or > V_(COLD). When V_(COOL) < V_(TS) < V_(COLD), the charging current is reduced to half of the programmed charge current. When V_(HOT) < V_(TS) < V_(WARM), the battery regulation voltage is reduced by 140 mV the programmed charge current.

The TS function is voltage based for maximum flexibility. Connect a resistor divider from V_IN to GND with TS connected to the center tap to set the threshold. The connections are shown in Figure 16. The resistor values are calculated using Equation 1 and Equation 2. To disable the TS function, pull TS above TS_OFF threshold.

Figure 16. TS Circuit

Equation 1.

Equation 2.

Where

• R_(HOT) = the NTC resistance at the hot temperature
• R_(COLD) = the NTC resistance at the cold temperature

The warm and cool thresholds are not independently programmable. The cool and warm NTC resistances for a selected resistor devider are calculated using Equation 3 and Equation 4.

Equation 3.

Equation 4.

9.3.17 Thermal Protection

During the charging process, to prevent overheating in the device, the juntion temperature of the die, T_J, is monitored. When T_J reaches T_(SHUTDOWN) the device stops charging, disables the PMID output, disables the SYS output, and disables the LS/LDO output. During the time that T_(SHUTDOWN) is exceeded, the safety timer is reset and the watchdog timer continues to operate if in host mode. The charge cycle resumes when T_J falls below T_(SHUTDOWN) by T_(HYS).

To avoid reaching thremal shutdown, ensure that the system power dissipation is under the limits of the device. The power dissipated by the device can be calculated using Equation 5.

Where

• P_(BLOCK) = (V_IN – V_(PMID)) x I_IN
• P_(SYS) = I_SYS² x R_{DS(ON_HS)}
• P_(LS/LDO) = (V_(INLS) – V_(LS/LDO)) x I_(LS/LDO)
• P_(BAT) = (V_(PMID) – V_(BAT)) x I_(BAT)

9.3.18 Typical Application Power Dissipation

The die junction temperature, T_J, can be estimated based on the expected board performance using Equation 6.

The θ_JA is largely driven by the board layout. For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report SPRA953. Under typical conditions, the time spent in this state is short.

9.3.19 Status Indicators (PG and INT)

The device contains two open-drain outputs that signal its status and are valid only after the device has completed start-up into a valid state. If the part starts into a fault, interrupts will not be sent. The PG output signals when a valid input source is connected.  PG pulls to GND when V_IN is above V_UVLO. PG is high-impedance when the input power is not within specified limits. Connect PG to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor, or use with an LED for visual indication.

The PG pin can be configured as a MR shifted (MRS) output when the PGB_MRS bit is set to 1. PG is high-impedance when the MR input is not low, and PG pulls to GND when the MR input is below V_{OL(TH_MRS)}. Connect PG to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor.

When enabled through OTP, the PG pin also functions as an OVP/UVP indicator. When the device is below V_SLP or V_IN(DPM) (if enabled), a single 128us pulse is sent on PG to notify the host, repeating once per minute. When the device has an input voltage greater than V_(BAT) +1 V and V_IN is less than V_OVP, two consecutive 128us pulses are sent on PG, to notify the host, repeating once per minute. The PG pin does not function as an input power good indicator in this mode.

The INT pin is pulled low during charging when the EN_INT bit is set to 1 and interrupts are pulled high. When EN_INT is set to 0, charging status is not indicated on the INT pin. When charge is complete or disabled, INT is high impedance. The charge status is valid whether it is the first charge or recharge.  When a fault occurs, a 128 µs pulse (interrupt) is sent on INT to notify the host.

9.3.20 Chip Disable (CD)

The device contains a CD input that is used to disable the device and place it into a high impedance mode when only battery is present. In this case, when CD is low, PMID and SYS remain active, and the battery discharge FET is turned on. If the LS/LDO output has been enabled prior to pulling CD low, it will stay on. The LSCTRL pin can also enable/disable the LS/LDO output when the CD pin is pulled low. The CD pin has an internal pull-down.

If V_IN is present and the CD input is pulled low, charge is enabled and all other functions remain active. If V_IN is present and the CD input is pulled high, charge is disabled.

9.3.21 Buck (PWM) Output

The device integrates a low quiscent current switching regulator with DCS control allowing high efficiency down to 10-µA load currents. DCS control combines the advantages of hysteretic and voltage mode control. The internally compensated regulation network achieves fast and stable operation with small external components and low ESR capacitors. During PWM mode, it operates in continuous conduction mode, with a frequency up to 2 MHz. If the load current decreases, the converter enters a power save mode to maintain high efficiency down to light loads. In this mode, the device generates a single switching pulse to ramp up the inductor current and recharge the output capacitor, followed by a sleep period where most of the internal circuits are shut down to achieve a low quiescent current. The duration of the sleep period depends on the load current and the inductor peak current.

The output voltage is programmable using the SYS_SEL and SYS_VOUT bits in the SYS VOUT control register.

The SW output is enabled using the EN_SYS_OUT bit in the register. This bit is for testing and debug only and not intended to be used in the final system. When the device is enabled, the internal reference is powered up and the device enters softstart, starts switching, and ramps up the output voltage. When SW is disabled, the output is in shutdown mode in a low quiescent state. The device provides automatic output voltage discharge so the output voltage will ramp up from zero once the device in enabled again. Once SYS has been disabled, either V_IN needs to be connected or the MR button must be held low for the t_RESET duration to re-enable SYS.

The output is optimized for operation with a 2.2-µH inductor and 10-µF output capacitor. Table 6 shows the recommended LC output filter combinations.

The inductor value affects the peak-to-peak ripple current, the PWM-to-PFM transition point where the part enters and exits Pulse Frequency Modulation to lower the power consumed at low loads, the output voltage ripple and the efficiency. The selected inductor must be selected for its DC resistance and saturation current. The inductor ripple current (ΔI_L) can be estimated according to Equation 7.

Use Equation 8 to calculate the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current. As the size of the inductor decreases, the saturation “knee” must be carefully considered to ensure that the inductance does not decrease during higher load condition or transient. This is recommended because during a heavy load transient the inductor current rises above the calculated value. A more conservative way is to select the inductor saturation current above the high-side MOSFET switch current.

Where

• F = Switching Frequency
• L = Inductor Value
• ΔI_L = Peak to Peak inductor ripple current
• I_L(max) = Maximum Inductor current

In DC/DC converter applications, the efficiency is affected by the inductor AC resistance and by the inductor DCR value.

Table 7 shows recommended inductor series from different suppliers.

The PWM allows the use of small ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. The output capacitor requires either an X7R or X5R dielectric. At light load currents, the converter operates in Power Save Mode and the output voltage ripple is dependent on the output capacitor value and the PFM peak inductor current. Because the PWM converter has a pulsating input current, a low ESR input capacitor is required on PMID for the best voltage filtering to ensure proper function of the device and to minimize input voltage spikes. For most applications a 10-µF capacitor value is sufficient. The PMID capacitor can be increased to 22 µF for better input voltage filtering.

Table 8 shows the recommended input/output capacitors.

9.3.22 Load Switch / LDO Output and Control

The device integrates a low Iq load switch which can also be used as a regulated output. The LSCTRL pin can be used to turn the load on or off. Activating LSCTRL continuously holds the switch in the on state so long as there is not a fault. The signal is active HI and has a low threshold making it capable of interfacing with low voltage signals. To limit voltage drop or voltage transients, a small ceramic capacitor must be placed close to VINLS. Due to the body diode of the PMOS switch, it is recommended to have the capacitor on VINLS ten times larger than the output capacitor on LS/LDO.

The output voltage is programmable using the LS_LDO bits in the register. The LS/LDO voltage is calculated using Equation 9.

If a value greater than 3.3 V is written, the setting goes to pass-through mode where LS/LDO = VINLS - V_(DROPOUT). Table 9 summarizes the control of the LS/LDO output based on the I²C or LSCTRL pin setting:

If the output of the LDO is less than the programmed V_(SYS) voltage, connect VINLS to SYS. If the output of the LDO is greater than the programmed V_SYS voltage, connect VINLS to PMID.

The current capability of the LDO depends on the VINLS input voltage and the programmed output voltage. The full 100-mA output current for 0.8-V output voltage can be achieved when V_(VINLS) > 3.25 V. The full 100-mA output current for 3.3-V output voltage can be achieved when V_(VINLS) > 3.6 V.

When the LSLDO output is disabled with LSCTRL or through the register, an internal pull-down discharges the output.

9.3.23 Manual Reset Timer and Reset Output (MR and RESET)

The MR input has an internal pull-up to BAT, and MR is functional only when BAT is present or when VIN is valid, stable, and charge is enabled. If MR input is asserted during a transient condition while VIN ramps up the IC may incorrectly turn off the SYS buck output, therefore MR should not be asserted during this condition in order to avoid unwanted shutdown of SYS output rail. The input conditions can be adjusted by using MRWAKE bits for the wake conditions and MRRESET bits for the reset conditions. When a wake condition is met, a 128-µs pulse is sent on INT to notify the host, and the WAKE1 and/or WAKE2 bits are updated on I²C. The MR_WAKE bits and RESET FAULT bits are not cleared until the Push-button Control Register is read from I²C.  

When a MR reset condition is met, a 128us pulse is sent on INT to notify the host and a RESET signal is asserted. A reset pulse occurs with duration of t_{RESET_D} only one time after each valid MRRESET condition. The MR pin must be released (go high) and then driven low for the MRWAKE period before RESET asserts again. After RESET is asserted with battery only present, the device enters either Ship mode or Hi-Z mode depending on MRREC register settings. After RESET is asserted with a valid V_IN present, the device resumes operation prior to the MR button press.  If SYS was disabled prior to RESET, the SYS output is re-enabled if recovering into Hi-Z or Active Battery.

The MRRESET_VIN register can be configured to have RESET asserted by a button press only, or by a button press and V_IN present (V_UVLO + V_SLP < V_IN < V_OVP).

Table 10. Modes and Functions

Table 11. Fault and Status Condition Responses

9.5.1 Serial Interface Description

The device uses an I²C compatible interface to program and read many parameters. I²C is a 2-wire serial interface developed by NXP. The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus through open drain I/O terminals, SDA and SCL. A master device, usually a microcontroller or digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device.

The device works as a slave and supports the following data transfer modes, as defined in the I²C BUS Specification: standard mode (100 kbps) and fast mode (400kbps). The interface adds flexibility to the battery management solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. The I²C circuitry is powered from the battery in active battery mode. The battery voltage must stay above V_(BATUVLO) when no V_IN is present to maintain proper operation.

The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the F/S-mode in this document. The device only supports 7-bit addressing. The device 7-bit address is 6A (8-bit shifted address is D4).

To avoid I²C hang-ups, a timer (t_I2CRESET) runs duringI²C transactions. If the SDA line is held low longer than t_I2CRESET, any additional commands are ignored and the I²C engine is reset. The timeout is reset with START and repeated START conditions and stops when a valid STOP condition is sent.

9.5.2 F/S Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 19. All I²C-compatible devices should recognize a start condition.

Figure 19. Start Stop Condition

The master then generates the SCL pulses, and transmits the address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 20). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates and acknowledge (see Figure 21) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting the acknowledge, the master knows that communication link with a slave has been established.

Figure 20. Bit Transfer on the Serial Interface

Figure 21. Acknowledge on the I²C Bus

The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. An acknowledge signal can either be generated by the master or by the slave, depending on which on is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 22). This releases the bus and stops the communication link with the addressed slave. All I²C compatible devices must recognize the STOP condition. Upon the receipt of a STOP condition, all devices know that the bus is released, and wait for a START condition followed by a matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the slave I²C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in this section results in 0xFFh being read out.

Figure 22. Bus Protocol

9.6.1 Status and Ship Mode Control Register

Memory location 0x00h, Reset State: xx0x xxx1 (bq25120)

9.6.2 Faults and Faults Mask Register

Memory location 0x01h, Reset State: xxxx 0000 (bq25120)

9.6.3 TS Control and Faults Masks Register

Memory location 0x02h, Reset State: 1xxx 1000 (bq25120)

9.6.4 Fast Charge Control Register

Memory location 0x03h, Reset State: 0001 0100 (bq25120)

9.6.5 Termination/Pre-Charge and I²C Address Register

Memory location 0x04h, Reset State: 0000 1110 (bq25120)

9.6.6 Battery Voltage Control Register

Memory location 0x05h, Reset State: 0111 1000 (bq25120)

9.6.7 SYS VOUT Control Register

Memory location 0x06h, Reset State: 1010 1010 (bq25120)

9.6.8 Load Switch and LDO Control Register

Memory location 0x07h, Reset State: 0111 110x (bq25120)

9.6.9 Push-button Control Register

Memory location 0x08h, Reset State: 0110 10xx (bq25120)

9.6.10 ILIM and Battery UVLO Control Register

Memory location 0x09h, Reset State: 0000 1010 (bq25120)

9.6.11 Voltage Based Battery Monitor Register

Memory location 0x0Ah, Reset State: 0xxx xxxx (bq25120)

9.6.12 VIN_DPM and Timers Register

Memory location 0x0Bh, Reset State: 0100 1010 (bq25120)