SLUSD33A November 2017 – January 2021 BQ25122
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
INPUT CURRENTS | |||||||
IIN | Supply Current for Control | V(UVLO) < VIN < V(OVP) and VIN > V(BAT) + V(SLP) PWM Switching, –40 < TJ < 85 | 1 | mA | |||
V(UVLO) < VIN < V(OVP) and VIN > V(BAT) + V(SLP) PWM NOT Switching | 3 | mA | |||||
0°C < TJ < 85°C, VIN = 5 V, Charge Disabled | 1.5 | mA | |||||
I(BAT_HIZ) | Battery discharge current in High Impedance Mode | 0°C < TJ < 60°C, VIN = 0 V, High-Z Mode, PWM Not Switching, V(BUVLO) < V(BAT) < 4.65V | 0.7 | 1.2 | µA | ||
0°C < TJ < 60°C, VIN = 0 V, High-Z Mode, PWM Not Switching, V(BUVLO) < V(BAT) < 6.6 V | 0.9 | 1.5 | µA | ||||
0°C < TJ < 60°C, VIN = 0 V or floating, High-Z Mode, PWM Switching, No Load | 0.75 | 3.5 | µA | ||||
0°C < TJ < 85°C, VIN = 0 V, High-Z Mode, PWM Switching, LSLDO enabled | 1.35 | 4.25 | µA | ||||
I(BAT_ACTIVE) | Battery discharge current in Active Battery Mode | 0°C < TJ < 85°C, VIN = 0 V, Active Battery Mode, PWM Switching, LSLDO enabled, I2C Enabled, V(BUVLO) < V(BAT) < 4.65 V | 6.8 | 12 | µA | ||
0°C < TJ < 85°C, 0 < VIN < VIN(UVLO), Active Battery Mode, PWM Switching, LSLDO disabled, I2C Enabled, /CD = Low, V(BUVLO) < V(BAT) < 4.65 V | 6.2 | 11 | µA | ||||
I(BAT_SHIP) | Battery discharge current in Ship Mode | 0°C < TJ < 85°C, VIN = 0 V, Ship Mode | 2 | 150 | nA | ||
POWER-PATH MANAGEMENT and INPUT CURRENT LIMIT | |||||||
VDO(IN-PMID) | VIN – V(PMID) | VIN = 5 V, IIN = 300 mA | 125 | 170 | mV | ||
VDO(BAT-PMID) | V(BAT) – V(PMID) | VIN = 0 V, V(BAT) > 3 V, Iff = 400 mA | 120 | 160 | mV | ||
V(BSUP1) | Enter supplement mode threshold | V(BAT) > V(BUVLO) | V(PMID) < V(BAT) – 25 mV | V | |||
V(BSUP2) | Exit supplement mode threshold | V(BAT) > V(BUVLO) | V(PMID) < V(BAT) – 5mV | V | |||
I(BAT_OCP) | Current Limit, Discharge Mode | V(BAT) > V(BUVLO) | 0.85 | 1.15 | 1.35 | A | |
I(ILIM) | Input Current Limit | Programmable Range, 50-mA steps | 50 | 400 | mA | ||
Maximum Input Current using ILIM | K(ILIM) / R(ILIM) | ||||||
IILIM accuracy IILIM accuracy | 50 mA to 100 mA | –12% | 12% | ||||
100 mA to 400 mA | –5% | 5% | |||||
K(ILIM) | Maximum input current factor | I(ILIM) = 50 mA to 100 mA | 175 | 200 | 225 | AΩ | |
I(ILIM) = 100 mA to 400 mA | 190 | 200 | 210 | AΩ | |||
VIN(DPM) | Input voltage threshold when input current is reduced | Programmable Range using VIN(DPM) Registers. Can be disabled using VIN(DPM_ON) | 4.2 | 4.9 | V | ||
VIN_DPM threshold accuracy | –3% | 3% | |||||
BATTERY CHARGER | |||||||
V(DPPM) | PMID voltage threshold when charge current is reduced | Above V(BATREG) | 0.2 | V | |||
RON(BAT-PMID) | Internal Battery Charger MOSFET on-resistance | Measured from BAT to PMID, V(BAT) = 4.35 V, High-Z mode | 300 | 400 | mΩ | ||
V(BATREG) | Charge Voltage | Operating in voltage regulation, Programmable Range, 10mV steps | 3.6 | 4.65 | V | ||
Voltage Regulation Accuracy | TJ = 25°C | –0.5% | 0.5% | ||||
TJ = 0°C to 85°C | –0.5% | 0.5% | |||||
I(CHARGE) | Fast Charge Current Range | V(BATUVLO) < V(BAT) < V(BATREG) | 5 | 300 | mA | ||
Fast Charge Current using ISET | K(ISET) / R(ISET) | A | |||||
Fast Charge Current Accuracy | –5% | 5% | |||||
K(ISET) | Fast Charge Current Factor | 5 mA > I(CHARGE) > 300 mA | 190 | 200 | 210 | AΩ | |
I(TERM) | Termination charge current | Termination current programmable range over I2C | 0.5 | 37 | mA | ||
Termination Current using IPRETERM | I(CHARGE) < 300 mA, R(ITERM) = 15 kΩ | 5 | % of ISET | ||||
I(CHARGE) < 300 mA, R(ITERM) = 4.99 kΩ | 10 | % of ISET | |||||
I(CHARGE) < 300 mA, R(ITERM) = 1.65 kΩ | 15 | % of ISET | |||||
I(CHARGE) < 300 mA, R(ITERM) = 549 Ω | 20 | % of ISET | |||||
Accuracy | I(TERM) > 4 mA | –10% | 10% | ||||
tDGL(TERM) | TERM deglitch time | Both rising and falling, 2-mV over-drive, tRISE, tFALL = 100 ns | 64 | ms | |||
I(PRE_CHARGE) | Pre-charge current | Pre-charge current programmable range over I2C | 0.5 | 37 | mA | ||
Pre-charge Current using IPRETERM | I(TERM) | A | |||||
Accuracy | –10% | 10% | |||||
V(RCH) | Recharge threshold voltage | Below V(BATREG) | 100 | 120 | 140 | mV | |
tDGL(RCHG) | Recharge threshold deglitch time | tFALL = 100 ns typ, V(RCH) falling | 32 | ms | |||
SYS OUTPUT | |||||||
RDS(ON_HS) | PMID = 3.6 V, I(SYS) = 150 mA | 675 | 850 | mΩ | |||
RDS(ON_LS) | PMID = 3.6 V, I(SYS) = 150 mA | 300 | 475 | mΩ | |||
RDS(CH_SYS) | MOSFET on-resistance for SYS discharge | VIN = 3.6 V, IOUT = –10 mA into VOUT pin | 22 | 40 | Ω | ||
I(LIMF) | SW Current limit HS | 2.2V < V(PMID) < 5.5 V | 450 | 600 | 675 | mA | |
SW Current limit LS | 2.2V < V(PMID) < 5.5 V | 450 | 700 | 850 | mA | ||
I(LIM_SS) | PMOS switch current limit during softstart | Current limit is reduced during softstart | 80 | 130 | 200 | mA | |
VSYS | SYS Output Voltage Range | Programmable range, 100 mV Steps | 1.1 | 3.3 | V | ||
Output Voltage Accuracy | VIN = 5 V, PFM mode, IOUT = 10 mA, V(SYS) = 1.8 V | –2.5% | 0 | 2.5% | |||
DC Output Voltage Load Regulation in PWM mode | VOUT = 2 V, over load range | 0.01 | %/mA | ||||
DC Output Voltage Line Regulation in PWM mode | VOUT = 2.V, IOUT = 100 mA, over VIN range | 0.01 | %/V | ||||
LS/LDO OUTPUT | |||||||
VIN(LS) | Input voltage range for LS/LDO | Load Switch Mode | 0.8 | 6.6 | V | ||
Input voltage range for LS/LDO | LDO Mode | 2.2 | 6.6 | V | |||
VOUT | DC output accuracy | TJ = 25°C | –2% | ±1% | 2% | ||
Over VIN, IOUT, temperature | –3% | ±2% | 3% | ||||
VLDO | Output range for LS/LDO | Programmable Range, 0.1 V steps | 0.8 | 3.3 | V | ||
ΔVOUT / Δ VIN | DC Line regulation | VOUT(NOM) + 0.5 V < VIN < 6.6 V, IOUT = 5 mA | –1% | 1% | |||
DC Load regulation | 0 mA < IOUT < 100 mA | –1% | 1% | ||||
Load Transient | 2 uA to 100 mA, VOUT = 1. 8V | –120 | 60 | mV | |||
RDS(ON_LDO) | FET Rdson | V(VINLS) = 3.6 V | 570 | 800 | mΩ | ||
R(DSCH_LSLDO) | MOSFET on-resistance for LS/LDO discharge | 1.7V < V(VINLS) < 6.6 V, ILOAD = –10 mA | 20 | Ω | |||
I(OCL_LDO) | Output Current Limit – LDO | VLS/LDO = 0V | 275 | 365 | 475 | mA | |
I(LS/LDO) | Output Current | V(VINLS) = 3.6 V, VLSLDO = 3.3 V | 100 | mA | |||
V(VINLS) = 3.3 V, VLSLDO = 0.8 V | 100 | mA | |||||
V(VINLS) = 2.2 V, VLSLDO = 0.8 V | 10 | mA | |||||
IIN(LDO) | Quiescent current for VINLS in LDO mode | 0.9 | µA | ||||
OFF-state supply current | 0.25 | µA | |||||
VIH(LSCTRL) | High-level input voltage for LSCTRL | 1.15 V > V(VINLS) > 6.6 V | 0.75 x V(SYS) | 6.6 | V | ||
VIL(LSCTRL) | Low-level input voltage for LSCTRL | 1.15 V > V(VINLS) > 6.6 V | 0.25 x V(SYS) | V | |||
PUSHBUTTON TIMER ( MR) | |||||||
VIL | Low-level input voltage | VBAT > VBUVLO | 0.3 | V | |||
RPU | Internal pull-up resistance | 120 | kΩ | ||||
VBAT MONITOR | |||||||
VBMON | Battery Voltage Monitor Accuracy | V(BAT) Falling - Including 2% increment | –3.5 | 3.5 | %V(BATREG) | ||
BATTERY-PACK NTC MONITOR | |||||||
VHOT | High temperature threshold | VTS falling, 1% VIN Hysteresis | 14.5 | 15 | 15.2 | %VIN | |
VWARM | Warm temperature threshold | VTS falling, 1% VIN Hysteresis | 20.1 | 20.5 | 20.8 | %VIN | |
VCOOL | Cool temperature threshold | VTS rising, 1% VIN Hysteresis | 35.4 | 36 | 36.4 | %VIN | |
VCOLD | Low temperature threshold | VTS rising, 1% VIN Hysteresis | 39.3 | 39.8 | 40.2 | %VIN | |
TSOFF | TS Disable threshold | VTS rising, 2% VIN Hysteresis | 55 | 60 | %VIN | ||
PROTECTION | |||||||
V(UVLO) | IC active threshold voltage | VIN rising | 3.4 | 3.6 | 3.8 | V | |
VUVLO(HYS) | IC active hysteresis | VIN falling from above VUVLO | 150 | mV | |||
V(BUVLO) | Battery Undervoltage Lockout threshold Range | Programmable Range for V(BUVLO) VBAT falling, 150 mV Hysteresis | 2.2 | 3.0 | V | ||
Default Battery Undervoltage Lockout Accuracy | V(BAT) falling | –2.5% | 2.5% | ||||
V(BATSHORT) | Battery short circuit threshold | Battery voltage falling | 2 | V | |||
V(BATSHORT_HYS) | Hysteresis for V(BATSHORT) | 100 | mV | ||||
I(BATSHORT) | Battery short circuit charge current | I(PRETERM) | mA | ||||
V(SLP) | Sleep entry threshold, VIN – V(BAT) | 2 V < VBAT < V(BATREG), VIN falling | 65 | 120 | mV | ||
V(SLP_HYS) | Sleep-mode exit hysteresis | VIN rising above V(SLP) | 40 | 65 | 100 | mV | |
VOVP | Maximum Input Supply OVP threshold voltage | VIN rising, 100 mV hysteresis | 5.35 | 5.55 | 5.75 | V | |
tDGL_OVP | Deglitch time, VIN OVP falling | VIN falling below VOVP, 1V/us | 32 | ms | |||
TSHTDWN | Thermal trip | VIN > VUVLO | 114 | °C | |||
THYS | Thermal hysteresis | VIN > VUVLO | 11 | °C | |||
tDGL_SHTDWN | Deglitch time, Thermal shutdown | TJ rising above TSHTDWN | 4 | µs | |||
I2C INTERFACE | |||||||
I2C Bus Specification standard and fast mode frequency support | 100 | 400 | kHz | ||||
VIL | Input low threshold level | VPULLUP = 1.1 V, SDA and SCL | 0.275 | V | |||
VIH | Input high threshold level | VPULLUP = 1.1 V, SDA and SCL | 0.825 | V | |||
VIH | Input high threshold level | VPULLUP = 3.3 V, SDA and SCL | 2.475 | V | |||
VOL | Output low threshold level | IL = 5mA, sink current, VPULLUP = 1.1 V | 0.275 | V | |||
IBIAS | High-Level leakage current | VPULLUP = 1.8V, SDA and SCL | 1 | µA | |||
INT, PG, and RESET OUTPUT (Open Drain) | |||||||
VOL | Low level output threshold | Sinking current = 5 mA | 0.25 x V(SYS) | V | |||
IIN | Bias current into pin | Pin is high impedance, IOUT = 0 mA; TJ = –40°C to 60°C | 12 | nA | |||
VIN(BAT_DELTA) | Input voltage above VBAT where PG sends two 128 µs pulses each minute to signal the host of the input voltage status | VUVLO < VIN < VOVP | 0.825 | 1 | 1.15 | V | |
INPUT PIN ( CD LSCTRL) | |||||||
VIL(/CD_LSCTRL) | Input low threshold | V(PULLUP) = VSYS = 3.3 V | 0.25 * VSYS | V | |||
VIH(/CD_LSCTRL) | Input high threshold | V(PULLUP) = VSYS = 3.3 V | 0.75 * VSYS | V | |||
RPULLDOWN/CD | Internal pull-down resistance | 900 | kΩ | ||||
R(LSCTRL) | Internal pull-down resistance | 2 | MΩ |