SLUSDL9A June   2019  – January 2021 BQ25125

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Ship Mode
        1. 9.3.1.1 Ship Mode Entry and Exit
      2. 9.3.2  High Impedance Mode
      3. 9.3.3  Active Battery Only Connected
      4. 9.3.4  Voltage Based Battery Monitor
      5. 9.3.5  Sleep Mode
      6. 9.3.6  Input Voltage Based Dynamic Power Management (VIN(DPM))
      7. 9.3.7  Input Overvoltage Protection and Undervoltage Status Indication
      8. 9.3.8  Battery Charging Process and Charge Profile
      9. 9.3.9  Battery Supplement Mode
      10. 9.3.10 Default Mode
      11. 9.3.11 Termination and Pre-Charge Current Programming by External Components (IPRETERM)
      12. 9.3.12 Input Current Limit Programming by External Components (ILIM)
      13. 9.3.13 Charge Current Programming by External Components (ISET)
      14. 9.3.14 Safety Timer
      15. 9.3.15 External NTC Monitoring (TS)
      16. 9.3.16 Thermal Protection
      17. 9.3.17 Typical Application Power Dissipation
      18. 9.3.18 Status Indicators ( PG and INT)
      19. 9.3.19 Chip Disable ( CD)
      20. 9.3.20 Buck (PWM) Output
      21. 9.3.21 Load Switch / LDO Output and Control
      22. 9.3.22 Manual Reset Timer and Reset Output ( MR and RESET)
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 Serial Interface Description
      2. 9.5.2 F/S Mode Protocol
    6. 9.6 Register Maps
      1. 9.6.1  Status and Ship Mode Control Register
      2. 9.6.2  Faults and Faults Mask Register
      3. 9.6.3  TS Control and Faults Masks Register
      4. 9.6.4  Fast Charge Control Register
      5. 9.6.5  Termination/Pre-Charge Register
      6. 9.6.6  Battery Voltage Control Register
      7. 9.6.7  SYS VOUT Control Register
      8. 9.6.8  Load Switch and LDO Control Register
      9. 9.6.9  Push-button Control Register
      10. 9.6.10 ILIM and Battery UVLO Control Register
      11. 9.6.11 Voltage Based Battery Monitor Register
      12. 9.6.12 VIN_DPM and Timers Register
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Default Settings
        2. 10.2.2.2 Choose the Correct Inductance and Capacitance
        3. 10.2.2.3 Calculations
          1. 10.2.2.3.1 Program the Fast Charge Current (ISET)
          2. 10.2.2.3.2 Program the Input Current Limit (ILIM)
          3. 10.2.2.3.3 Program the Pre-charge/termination Threshold (IPRETERM)
          4. 10.2.2.3.4 TS Resistors (TS)
      3. 10.2.3 Application Performance Curves
        1. 10.2.3.1 Charger Curves
        2. 10.2.3.2 SYS Output Curves
        3. 10.2.3.3 Load Switch and LDO Curves
        4. 10.2.3.4 LS/LDO Output Curves
        5. 10.2.3.5 Timing Waveforms Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.22 Manual Reset Timer and Reset Output ( MR and RESET)

The MR input has an internal pull-up to BAT, and MR is functional only when BAT is present or when VIN is valid, stable, and charge is enabled. If MR input is asserted during a transient condition while VIN ramps up the IC may incorrectly turn off the SYS buck output, therefore MR should not be asserted during this condition in order to avoid unwanted shutdown of SYS output rail.The input conditions can be adjusted by using MRWAKE bits for the wake conditions and MRRESET bits for the reset conditions. When a wake condition is met, a 128-µs pulse is sent on INT to notify the host, and the WAKE1 and/or WAKE2 bits are updated on I2C. The MR_WAKE bits and RESET FAULT bits are not cleared until the Push-button Control Register is read from I2C.  

When a MR reset condition is met, a 128-µs pulse is sent on INT to notify the host and a RESET signal is asserted. A reset pulse occurs with duration of tRESET_D only one time after each valid MRRESET condition. The MR pin must be released (go high) and then driven low for the MRWAKE period before RESET asserts again. After RESET is asserted with battery only present, the device enters either Ship mode or Hi-Z mode depending on MRREC register settings. For details on how to properly enter Ship Mode through MR, see Section 9.3.1.1 section. After RESET is asserted with a valid VIN present, the device resumes operation prior to the MR button press.  If SYS was disabled prior to RESET, the SYS output is re-enabled if recovering into Hi-Z or Active Battery.

The MRRESET_VIN register can be configured to have RESET asserted by a button press only, or by a button press and VIN present (VUVLO + VSLP < VIN < VOVP).