SLUSF40A October   2024  – December 2024 BQ25190

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Battery Charging Process
        1. 7.1.1.1 Trickle Charge
        2. 7.1.1.2 Precharge
        3. 7.1.1.3 Fast Charge
        4. 7.1.1.4 Termination
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Based Dynamic Power Management (VINDPM)
      2. 7.3.2  Dynamic Power Path Management Mode (DPPM)
      3. 7.3.3  Battery Supplement Mode
      4. 7.3.4  Sleep Mode
      5. 7.3.5  SYS Power Control
        1. 7.3.5.1 SYS Pulldown Control
      6. 7.3.6  SYS Regulation
      7. 7.3.7  ILIM Control
      8. 7.3.8  Protection Mechanisms
        1. 7.3.8.1  Input Overvoltage Protection
        2. 7.3.8.2  System Short Protection
        3. 7.3.8.3  Battery Depletion Protection
          1. 7.3.8.3.1 Battery Undervoltage Lockout
        4. 7.3.8.4  Battery Overcurrent Protection
        5. 7.3.8.5  Safety Timer and Watchdog Timer
        6. 7.3.8.6  Buck Overcurrent Protection
        7. 7.3.8.7  LDO Overcurrent Protection
        8. 7.3.8.8  Buck-Boost Overcurrent Protection
        9. 7.3.8.9  Buck-Boost Output Short-Circuit Protection
        10. 7.3.8.10 Buck/Buck-Boost/LDO Undervoltage Lockout
        11. 7.3.8.11 Sequence Undervoltage Lockout
        12. 7.3.8.12 Thermal Protection and Thermal Regulation
      9. 7.3.9  Integrated 12-Bit ADC for Monitoring
        1. 7.3.9.1 ADC Programmable Comparators
      10. 7.3.10 Pushbutton Wake and Reset Input
        1. 7.3.10.1 Pushbutton Short Button Press or Wake Functions
        2. 7.3.10.2 Pushbutton Long Button Press Functions
      11. 7.3.11 VIN Pulse Detection for Hardware Reset
      12. 7.3.12 15-Second VIN Watchdog for Hardware Reset
      13. 7.3.13 Hardware Reset
      14. 7.3.14 Software Reset
      15. 7.3.15 Interrupt to Host (INT)
      16. 7.3.16 External NTC Monitoring (TS)
        1. 7.3.16.1 TS Thresholds
      17. 7.3.17 Power Rail Power Sequence
        1. 7.3.17.1 Power-Up Sequence
        2. 7.3.17.2 Power-Down Sequence
      18. 7.3.18 Integrated Buck Converter (Buck)
      19. 7.3.19 Integrated Buck-Boost Converter (Buck-boost)
      20. 7.3.20 Integrated LDOs (LDO1/LDO2)
      21. 7.3.21 Multi-Function GPIOs
        1. 7.3.21.1 GPIO1 Functions
        2. 7.3.21.2 GPIO2 Functions
        3. 7.3.21.3 GPIO3 Functions
        4. 7.3.21.4 GPIO4 Functions
    4. 7.4 Device Functional Modes
      1. 7.4.1 Ship Mode
        1. 7.4.1.1 LDO1-ON Ship Mode
      2. 7.4.2 Battery Mode
      3. 7.4.3 Adapter Mode
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 START and STOP Conditions
        3. 7.5.1.3 Byte Format
        4. 7.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 7.5.1.5 Target Address and Data Direction Bit
        6. 7.5.1.6 Single Write and Read
        7. 7.5.1.7 Multi-Write and Multi-Read
    6. 7.6 Register Maps
      1. 7.6.1 BQ25190 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor Selection
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Recommended Passive Components
      3. 8.2.3 Application Performance Plots
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YBG|30
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.9 Integrated 12-Bit ADC for Monitoring

The device provides an integrated 12-bit ADC for the host to monitor various system parameters. The ADC_RATE bits allow continuous conversion, conversion every 1 second, conversion every 1 minute, and one-shot behavior.

To enable the ADC, the ADC_EN bit must be set to ‘1’. The ADC is disabled by default (ADC_EN=0) to conserve power. The ADC is allowed to operate if either VIN>VIN_UVLO or VBAT>VBAT_ADC_LOWVZ. In battery mode, if ADC_EN is written to '1' by the host with VBAT < VBAT_LOWVZ_ADC, it will then be automatically cleared. ADC_EN should not be set to 1 when no channel is enabled.

The ADC range for VIN is dependent on the VIN_OVP bit.

The ADC supports averaging by setting ADC_AVG = 1. In averaging mode, each new sample is averaged with the previous value of that channel's output register. When ADC_AVG_INIT = 1, the first converted value is stored without averaging, and each subsequent value is averaged. In this mode, the first stored value is X0, the second value is (½ X1 + ½ X0) and the third stored value is (½ X2 + ¼ X1 + ¼ X0), where X0, X1 and X2 are the sequential values measured by the ADC. When ADC_AVG = 1 and ADC_AVG_INIT = 1 in one-shot mode, two samples are taken and averaged.

The ADC_DONE_STAT and ADC_DONE_FLAG bits will be set when a conversion is complete in one-shot mode, every 1 second mode, and every 1 minute mode. During continuous conversion mode, the ADC_DONE_STAT and ADC_DONE_FLAG bits have no meaning and will remain at 0. In one-shot mode, the ADC_EN bit will be set to 0 at the completion of the conversion, at the same time as the ADC_DONE_FLAG bit is set and a 128-μs pulse is sent on INT pin to notify the host. In continuous mode, the ADC_EN bit remains at 1 until the user disables the ADC by setting it to 0. In conversion every 1 second mode and conversion every 1 minute mode mode, the ADC_IN bit stays high in the waiting period in between measurements, but the digital signal will turn off the ADC in the background to save power. After an one-shot ADC cycle is done, the user should wait for at least 25ms before setting ADC_RATE to continuous and enable ADC by setting ADC_EN to 1.

ADC conversion operates independently of the faults present in the device. ADC conversion will continue even when a fault has occurred, with the exception of the TSHUT fault, which disables the ADC until the fault clears.

The device has an ADCIN input to monitor the value of an external voltage signal up to 5V or support another NTC thermister measurement without the need of an external biasing circuit by setting ADCIN_MODE bit to '1'. In this mode, the ADCIN pin is biased with 80μA bias current, same as TS pin, and VADCIN is monitored up to 1V.

The TDIE and IBAT ADC channel registers report in 2's compliment format in order to represent positive and negative current. 16-bit registers in 2's compliment represent positive numbers using the range 0x0000 - 0x7FFF, with 0x0 representing 0 and 0x7FFF representing the maximum positive value of 32,767. The negative numbers are represented in the range 0x8000-0xFFFF with 0x8000 representing the most negative value of -32,768 and 0xFFFF representing -1. Note that these are the raw integer values of the register. To convert into the current reading of the ADC, multiply this integer by the scaling factor of the register.