SLUSF40 October   2024 BQ25190

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Battery Charging Process
        1. 7.1.1.1 Trickle Charge
        2. 7.1.1.2 Precharge
        3. 7.1.1.3 Fast Charge
        4. 7.1.1.4 Termination
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Based Dynamic Power Management (VINDPM)
      2. 7.3.2  Dynamic Power Path Management Mode (DPPM)
      3. 7.3.3  Battery Supplement Mode
      4. 7.3.4  Sleep Mode
      5. 7.3.5  SYS Power Control
        1. 7.3.5.1 SYS Pulldown Control
      6. 7.3.6  SYS Regulation
      7. 7.3.7  ILIM Control
      8. 7.3.8  Protection Mechanisms
        1. 7.3.8.1  Input Overvoltage Protection
        2. 7.3.8.2  System Short Protection
        3. 7.3.8.3  Battery Depletion Protection
          1. 7.3.8.3.1 Battery Undervoltage Lockout
        4. 7.3.8.4  Battery Overcurrent Protection
        5. 7.3.8.5  Safety Timer and Watchdog Timer
        6. 7.3.8.6  Buck Overcurrent Protection
        7. 7.3.8.7  LDO Overcurrent Protection
        8. 7.3.8.8  Buck-Boost Overcurrent Protection
        9. 7.3.8.9  Buck-Boost Output Short-Circuit Protection
        10. 7.3.8.10 Buck/Buck-Boost/LDO Undervoltage Lockout
        11. 7.3.8.11 Sequence Undervoltage Lockout
        12. 7.3.8.12 Thermal Protection and Thermal Regulation
      9. 7.3.9  Integrated 12-Bit ADC for Monitoring
        1. 7.3.9.1 ADC Programmable Comparators
      10. 7.3.10 Pushbutton Wake and Reset Input
        1. 7.3.10.1 Pushbutton Short Button Press or Wake Functions
        2. 7.3.10.2 Pushbutton Long Button Press Functions
      11. 7.3.11 VIN Pulse Detection for Hardware Reset
      12. 7.3.12 15-Second VIN Watchdog for Hardware Reset
      13. 7.3.13 Hardware Reset
      14. 7.3.14 Software Reset
      15. 7.3.15 Interrupt to Host (INT)
      16. 7.3.16 External NTC Monitoring (TS)
        1. 7.3.16.1 TS Thresholds
      17. 7.3.17 Power Rail Power Sequence
        1. 7.3.17.1 Power-Up Sequence
        2. 7.3.17.2 Power-Down Sequence
      18. 7.3.18 Integrated Buck Converter (Buck)
      19. 7.3.19 Integrated Buck-Boost Converter (Buck-boost)
      20. 7.3.20 Integrated LDOs (LDO1/LDO2)
      21. 7.3.21 Multi-Function GPIOs
        1. 7.3.21.1 GPIO1 Functions
        2. 7.3.21.2 GPIO2 Functions
        3. 7.3.21.3 GPIO3 Functions
        4. 7.3.21.4 GPIO4 Functions
    4. 7.4 Device Functional Modes
      1. 7.4.1 Ship Mode
        1. 7.4.1.1 LDO1-ON Ship Mode
      2. 7.4.2 Battery Mode
      3. 7.4.3 Adapter Mode
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 START and STOP Conditions
        3. 7.5.1.3 Byte Format
        4. 7.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 7.5.1.5 Target Address and Data Direction Bit
        6. 7.5.1.6 Single Write and Read
        7. 7.5.1.7 Multi-Write and Multi-Read
    6. 7.6 Register Maps
      1. 7.6.1 BQ25190 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor Selection
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Recommended Passive Components
      3. 8.2.3 Application Performance Plots
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YBG|30
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.8.12 Thermal Protection and Thermal Regulation

During operation, to protect the device from damage due to overheating, the junction temperature of the die is monitored.

In adapter mode, the TSHUT fault is triggered when TJ reaches TSHUT_RISING, or TJ_BUCK reaches TSHUT_RISING_BUCK if Buck is enabled, or TJ_BB reaches TSHUT_RISING_BB if Buck-boost is enabled, or TJ_LDO1 reaches TSHUT_RISING_LDO1 if LDO1 is enabled, or TJ_LDO2 reaches TSHUT_RISING_LDO2 if LDO2 is enabled. In this case, the device stops charging, disables all the operating power rails, and then turns off input FETs and BATFET. After tTSHUT_DGLZ, if TJ is below TSHUT_FALLING, the input FETs and BATFET are turned on to power SYS and charging can be restarted. The integrated power rails are reenabled when TSHUT fault recovers. The power-up sequence is implemented if power sequence is used with VSYS>VSEQ_UVLOZ.

In battery mode with ADC disabled (ADC_EN = 0), the TSHUT fault is triggered when TJ_BUCK reaches TSHUT_RISING_BUCK if Buck is enabled, or TJ_BB reaches TSHUT_RISING_BB if Buck-boost is enabled, or TJ_LDO1 reaches TSHUT_RISING_LDO1 if LDO1 is enabled, or TJ_LDO2 reaches TSHUT_RISING_LDO2 if LDO2 is enabled. In this case, the device disables all the operating power rails. After tTSHUT_DGLZ, the BATFET is turned on to power SYS. The integrated power rails are reenabled when TSHUT fault recovers. The power-up sequence is implemented if power sequence is used with VSYS>VSEQ_UVLOZ.

In battery only mode with ADC disabled (ADC_EN = 1), the TSHUT fault is triggered when TJ reaches TSHUT_RISING , or TJ_BUCK reaches TSHUT_RISING_BUCK if Buck is enabled, or TJ_BB reaches TSHUT_RISING_BB if Buck-boost is enabled, or TJ_LDO1 reaches TSHUT_RISING_LDO1 if LDO1 is enabled, or TJ_LDO2 reaches TSHUT_RISING_LDO2 if LDO2 is enabled. In this case, the device disables all the operating power rails, and then turns off the BATFET. After tTSHUT_DGLZ, if TJ is below TSHUT_FALLING, the BATFET is turned on to power SYS. The integrated power rails are reenabled when TSHUT fault recovers. The power-up sequence is implemented if power sequence is used with VSYS>VSEQ_UVLOZ.

The Buck thermal shutdown protection is not active in PFM mode and LDO1/LDO2 thermal shutdown is not active with load less than 1 mA.

When TSHUT fault is triggered, TSHUT_STAT/TSHUT_FLAG is set to 1 with interrupt signal sent from INT pin if TSHUT_MASK is not set to 1.

If TSHUT_LOCKOUT_EN is set to 1, the device is locked out in TSHUT protection (input FETs off, BATFET off, rails disabled) if TSHUT fault is triggered 7 to 13 times in the 2s window. Once the device is locked out in TSHUT protection, VIN needs to be toggled to bring the device out of the lock-out state after tTSHUT_DGLZ. After tTSHUT_DGLZ, if TJ is below TSHUT_FALLING, the input FETs or BATFET are able to be turned on to power SYS and charging can be restarted. The integrated power rails are reenabled when TSHUT fault recovers. The power-up sequence is implemented if power sequence is used with VSYS>VSEQ_UVLOZ.

When LDO1 is in always on mode (LDO1_EN_SET = b111) and LDO1_SHIP_AO is set to 1, the LDO1 is disabled only when TJ TJ reaches TSHUT_RISING_LOD1 and resumes operation when TJ falls below TSHUT_FALLING_LOD1. In LDO1-ON Ship mode, TSHUT_STAT/TSHUT_FLAG is not updated if the fault is triggered.

During the charging process, to prevent overheating in the device, the device monitors the junction temperature of the die and reduces the charging current once TJ reaches the thermal regulation threshold (TREG) based on bits set by THERM_REG setting. If the charge current is reduced to 0, the battery supplies the current needed to supply the SYS output. Thermal regulation can be disabled through I2C.

Four temperature settings are selectable in I2C and shown in Section 7.6.

The die junction temperature, TJ, can be estimated based on the expected board performance using the following equation:

TJ = TA + θJA * PDISS

The θJA is largely driven by the board layout. For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics Application Report.

For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating Conditions table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the thermal protection of the device is designed to protect against overheat conditions, it is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.