SLUSFD7 April   2024 BQ25308

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Power Up
        1. 8.3.1.1 Power-On-Reset (POR)
        2. 8.3.1.2 REGN Regulator Power Up
        3. 8.3.1.3 Charger Power Up
        4. 8.3.1.4 Charger Enable and Disable by EN Pin
        5. 8.3.1.5 Device Unplugged From Input Source
      2. 8.3.2 Battery Charging Management
        1. 8.3.2.1 Battery Charging Profile
        2. 8.3.2.2 Battery Charging Profile for LiFePO4
        3. 8.3.2.3 Precharge
        4. 8.3.2.4 Charging Termination
        5. 8.3.2.5 Battery Recharge
        6. 8.3.2.6 Charging Safety Timer
        7. 8.3.2.7 Thermistor Temperature Monitoring
      3. 8.3.3 Charging Status Indicator (STAT)
      4. 8.3.4 Protections
        1. 8.3.4.1 Voltage and Current Monitoring
          1. 8.3.4.1.1 Input Over-Voltage Protection
          2. 8.3.4.1.2 Input Voltage Dynamic Power Management (VINDPM)
          3. 8.3.4.1.3 Input Current Limit
          4. 8.3.4.1.4 Cycle-by-Cycle Current Limit
        2. 8.3.4.2 Thermal Regulation and Thermal Shutdown
        3. 8.3.4.3 Battery Protection
          1. 8.3.4.3.1 Battery Over-Voltage Protection (VBAT_OVP)
          2. 8.3.4.3.2 Dead Battery Charge Inhibit
        4. 8.3.4.4 ICHG Pin Open and Short Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable Mode, HiZ Mode, Sleep Mode, Charge Mode, Termination Mode, and Fault Mode
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Charge Voltage Settings
          2. 9.2.1.2.2 Charge Current Setting
          3. 9.2.1.2.3 Inductor Selection
          4. 9.2.1.2.4 Input Capacitor
          5. 9.2.1.2.5 Output Capacitor
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Typical Application with External Power Path
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RTE|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-6A0F7D7F-BEFE-4246-B6F6-F35338656A4C-low.gifFigure 6-1 RTE Package16-Pin WQFNTop View
Table 6-1 Pin Functions
PIN I/O(1) DESCRIPTION
NAME NO.
VBUS 1 P Charger input voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 2.2uF ceramic capacitor from VBUS to GND and place it as close as possible to IC.
PMID 16 P Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of high-side MOSFET (HSFET). Place ceramic 10μF on PMID to GND and place it as close as possible to IC.
SW 13,14 P Switching node. Connected to output inductor. Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047μF bootstrap capacitor from SW to BTST.
BTST 15 P High-side FET driver supply. Internally, the BTST is connected to the cathode of the internal boost-strap diode. Connect the 0.047μF bootstrap capacitor from SW to BTST.
GND 11,12 P Ground. Connected directly to thermal pad on the top layer. A single point connection is recommended between power ground and analog ground near the IC GND pins.
REGN 2 P Low-side FET driver positive supply output. Connect a 2.2μF ceramic capacitor from REGN to GND. The capacitor should be placed close to the IC.
BAT 10 AI Battery voltage sensing input. Connect this pin to the positive terminal of the battery pack and the node of inductor output terminal. 10-µF capacitor is recommended to connect to this pin.
TS 7 AI Battery temperature voltage input. Connect a negative temperature coefficient thermistor (NTC). Program temperature window with a resistor divider from REGN to TS and TS to GND. Charge suspends when TS pin voltage is out of range. When TS pin is not used, connect a 10-kΩ resistor from REGN to TS and a 10-kΩ resistor from TS to GND. It is recommended to use a 103AT-2 thermistor.
ICHG 4 AI Charge current program input. Connect a 1% resistor RICHG from this pin to ground to program the charge current as ICHG = KICHG / RICHG (KICHG = 40,000). No capacitor is allowed to connect at this pin. When the ICHG pin is pulled to ground or left open, the charger stops switching and the STAT pin starts blinking.
STAT 3 AO Charge status indication output. This pin is an open drain output. Connect this pin to REGN via a current limiting resistor and LED. The STAT pin indicates charger status as:
  • Charge in progress: STAT pin is pulled LOW
  • Charge completed, charge disabled by EN: STAT pin is OPEN
  • Fault conditions: STAT pin blinks
VSET 9 AI Charge voltage setting input. VSET pin sets battery charge voltage. Program battery regulation voltage with a resistor pull-down from VSET to GND as:
  • Floating (R > 200kΩ±10%): 3.6V
  • Shorted to GND (R < 510Ω): 4.05V
  • R = 51kΩ ± 10%: 4.15V
  • R = 10kΩ ± 10%: 4.2V
The maximum allowed capacitance on this pin is 50pF.
POL 5 AI EN pin polarity selection.
EN 6 AI Device disable input. With the POL pin floating, the device is enabled with the EN pin floating or pulled low, and the device is disabled if the EN pin is pulled high. With POL pin grounded, the device is enabled with the EN pin pulled high, and the device is disabled with the EN pin pulled low or floating.
NC 8 - No connection. Keep this pin floating or grounded.
Thermal Pad 17 - Ground reference for the device that is also the thermal pad used to conduct heat from the device. This connection serves two purposes. The first purpose is to provide an electrical ground connection for the device. The second purpose is to provide a low thermal-impedance path from the device die to the PCB. This pad should be tied externally to a ground plane. Ground layer(s) are connected to the thermal pad through vias under the thermal pad.
(1) AI = Analog Input, AO = Analog Output, AIO = Analog Input Output, DI = Digital Input, DO = Digital Output, DIO = Digital Input Output, P = Power