SLUSBJ3F August   2013  – March 2019

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Charger Efficiency
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Maximum Power Point Tracking
      2. 7.3.2 Battery Undervoltage Protection
      3. 7.3.3 Battery Overvoltage Protection
      4. 7.3.4 Battery Voltage in Operating Range (VBAT_OK Output)
      5. 7.3.5 Push-Pull Multiplexer Drivers
      6. 7.3.6 Nano-Power Management and Efficiency
    4. 7.4 Device Functional Modes
      1. 7.4.1 Main Boost Charger Disabled (Ship Mode) - (VSTOR > VSTOR_CHGEN and EN = HIGH)
      2. 7.4.2 Cold-Start Operation (VSTOR < VSTOR_CHGEN, VIN_DC > VIN(CS) and PIN > PIN(CS))
      3. 7.4.3 Main Boost Charger Enabled (VSTOR > VSTOR_CHGEN, VIN_DC > VIN(DC) and EN = LOW )
      4. 7.4.4 Thermal Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Energy Harvester Selection
      2. 8.1.2 Storage Element Selection
      3. 8.1.3 Inductor Selection
      4. 8.1.4 Capacitor Selection
        1. 8.1.4.1 VREF_SAMP Capacitance
        2. 8.1.4.2 VIN_DC Capacitance
        3. 8.1.4.3 VSTOR Capacitance
        4. 8.1.4.4 Additional Capacitance on VSTOR or VBAT_SEC
    2. 8.2 Typical Applications
      1. 8.2.1 Solar Application Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 TEG Application Circuit
      3. 8.2.3 Design Requirements
        1. 8.2.3.1 Detailed Design Procedure
        2. 8.2.3.2 Application Performance Plots
      4. 8.2.4 Piezoelectric Application Circuit
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
        3. 8.2.4.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Zip Files
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Thermal Information

THERMAL METRIC(1) bq25505 UNIT
RGR
20 PINS
θJA Junction-to-ambient thermal resistance 34.6 °C/W
θJCtop Junction-to-case (top) thermal resistance 49.0
θJB Junction-to-board thermal resistance 12.5
ψJT Junction-to-top characterization parameter 0.5
ψJB Junction-to-board characterization parameter 12.6
θJCbot Junction-to-case (bottom) thermal resistance 1.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.