SLUSCK5A
March 2017 – March 2023
BQ25601
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Description (continued)
6
Device Comparison Table
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Timing Requirements
8.7
Typical Characteristics
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Power-On-Reset (POR)
9.3.2
Device Power Up from Battery without Input Source
9.3.3
Power Up from Input Source
9.3.3.1
Power Up REGN Regulation
9.3.3.2
Poor Source Qualification
9.3.3.3
Input Source Type Detection
9.3.3.3.1
PSEL Pins Sets Input Current Limit in BQ25601
9.3.3.4
Input Voltage Limit Threshold Setting (VINDPM Threshold)
9.3.3.5
Converter Power Up
9.3.4
Boost Mode Operation From Battery
9.3.5
Host Mode and Standalone Power Management
9.3.5.1
Host Mode and Default Mode in BQ25601
9.3.6
Power Path Management
9.3.7
Battery Charging Management
9.3.7.1
Autonomous Charging Cycle
9.3.7.2
Battery Charging Profile
9.3.7.3
Charging Termination
9.3.7.4
Thermistor Qualification
9.3.7.5
JEITA Guideline Compliance During Charging Mode
9.3.7.6
Boost Mode Thermistor Monitor During Battery Discharge Mode
9.3.7.7
Charging Safety Timer
9.3.8
Protections
9.3.8.1
Voltage and Current Monitoring in Converter Operation
9.3.8.1.1
Voltage and Current Monitoring in Buck Mode
9.3.8.1.1.1
Input Overvoltage (ACOV)
9.3.8.1.1.2
System Overvoltage Protection (SYSOVP)
9.3.8.2
Voltage and Current Monitoring in Boost Mode
9.3.8.2.1
VBUS Soft Start
9.3.8.2.2
VBUS Output Protection
9.3.8.2.3
Boost Mode Overvoltage Protection
9.3.8.3
Thermal Regulation and Thermal Shutdown
9.3.8.3.1
Thermal Protection in Buck Mode
9.3.8.3.2
Thermal Protection in Boost Mode
9.3.8.4
Battery Protection
9.3.8.4.1
Battery Overvoltage Protection (BATOVP)
9.3.8.4.2
Battery Overdischarge Protection
9.3.8.4.3
System Overcurrent Protection
9.4
Device Functional Modes
9.4.1
Narrow VDC Architecture
9.4.2
Dynamic Power Management
9.4.3
Supplement Mode
9.4.4
Shipping Mode and QON Pin
9.4.4.1
BATFET Disable Mode (Shipping Mode)
9.4.4.2
BATFET Enable (Exit Shipping Mode)
9.4.4.3
BATFET Full System Reset
9.4.4.4
QON Pin Operations
9.4.5
Status Outputs ( PG, STAT, INT )
9.4.5.1
Power Good Indicator ( PG Pin and PG_STAT Bit)
9.4.5.2
Charging Status Indicator (STAT)
9.4.5.3
Interrupt to Host ( INT)
9.5
Programming
9.5.1
Serial Interface
9.5.1.1
Data Validity
9.5.1.2
START and STOP Conditions
9.5.1.3
Byte Format
9.5.1.4
Acknowledge (ACK) and Not Acknowledge (NACK)
9.5.1.5
Target Address and Data Direction Bit
9.5.1.6
Single Read and Write
9.5.1.7
Multi-Read and Multi-Write
9.6
Register Maps
9.6.1
REG00
9.6.2
REG01
9.6.3
REG02
9.6.4
REG03
9.6.5
REG04
9.6.6
REG05
9.6.7
REG06
9.6.8
REG07
9.6.9
REG08
9.6.10
REG09
9.6.11
REG0A
9.6.12
REG0B
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
Inductor Selection
10.2.2.2
Input Capacitor
10.2.2.3
Output Capacitor
10.2.3
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
Device and Documentation Support
13.1
Device Support
13.1.1
Third-Party Products Disclaimer
13.2
Documentation Support
13.2.1
Related Documentation
13.3
Receiving Notification of Documentation Updates
13.4
Support Resources
13.5
Trademarks
13.6
Electrostatic Discharge Caution
13.7
Glossary
14
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RTW|24
MPQF167C
Thermal pad, mechanical data (Package|Pins)
RTW|24
QFND125K
Orderable Information
slusck5a_oa
slusck5a_pm
10.2
Typical Application
Figure 10-1
Power Path Management Application