SLUSCK6C May   2017  – September 2021 BQ25606

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Device Power Up from Battery without Input Source
      2. 9.3.2 Power Up from Input Source
        1. 9.3.2.1 Power Up REGN Regulation
        2. 9.3.2.2 Poor Source Qualification
        3. 9.3.2.3 Input Source Type Detection
          1. 9.3.2.3.1 D+/D– Detection Sets Input Current Limit in BQ25606
        4. 9.3.2.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 9.3.2.5 Converter Power Up
      3. 9.3.3 Boost Mode Operation From Battery
      4. 9.3.4 Power Path Management
        1. 9.3.4.1 Narrow VDC Architecture
        2. 9.3.4.2 Dynamic Power Management
        3. 9.3.4.3 Supplement Mode
      5. 9.3.5 Battery Charging Management
        1. 9.3.5.1 Autonomous Charging Cycle
        2. 9.3.5.2 Charging Termination
        3. 9.3.5.3 Thermistor Qualification
        4. 9.3.5.4 JEITA Guideline Compliance During Charging Mode
        5. 9.3.5.5 Boost Mode Thermistor Monitor during Battery Discharge Mode
        6. 9.3.5.6 Charging Safety Timer
      6. 9.3.6 Status Outputs ( PG, STAT)
        1. 9.3.6.1 Power Good Indicator (PG Pin)
        2. 9.3.6.2 Charging Status Indicator (STAT)
      7. 9.3.7 Protections
        1. 9.3.7.1 Input Current Limit
        2. 9.3.7.2 Voltage and Current Monitoring in Converter Operation
          1. 9.3.7.2.1 Voltage and Current Monitoring in Buck Mode
            1. 9.3.7.2.1.1 Input Overvoltage (ACOV)
            2. 9.3.7.2.1.2 System Overvoltage Protection (SYSOVP)
        3. 9.3.7.3 Voltage and Current Monitoring in Boost Mode
          1. 9.3.7.3.1 VBUS Soft Start
          2. 9.3.7.3.2 VBUS Output Protection
          3. 9.3.7.3.3 Boost Mode Overvoltage Protection
        4. 9.3.7.4 Thermal Regulation and Thermal Shutdown
          1. 9.3.7.4.1 Thermal Protection in Buck Mode
          2. 9.3.7.4.2 Thermal Protection in Boost Mode
        5. 9.3.7.5 Battery Protection
          1. 9.3.7.5.1 Battery Overvoltage Protection (BATOVP)
          2. 9.3.7.5.2 Battery Overdischarge Protection
          3. 9.3.7.5.3 System Overcurrent Protection
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Input Capacitor
        3. 10.2.2.3 Output Capacitor
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Pin Configuration and Functions

GUID-899798D4-EBA0-477F-8B81-1F5E327357F2-low.gif Figure 7-1 BQ25606 RGE Package24-Pin VQFNTop View
Table 7-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
NC 2 No connection. This pin must be floating.
BAT 13 P Battery connection point to the positive terminal of the battery pack. The internal current sensing resistor is connected between SYS and BAT. Connect a 10-µF capacitor closely to the BAT pin.
14
BTST 21 P PWM high side driver positive supply. internally, the BTST is connected to the cathode of the boost-strap diode. Connect a 0.047-μF bootstrap capacitor from SW to BTST.
CE 9 DI Charge enable pin. When this pin is driven low, battery charging is enabled.
D+ 3 AIO Positive line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2 and nonstandard adaptors.
D– 4 AIO Negative line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2 and nonstandard adaptors.
GND 17 P Power ground and signal ground.
18
ICHG 10 AI ICHG pin sets the charge current limit. A resistor is connected from ICHG pin to ground to set charge current limit as ICHG = KICHG/RICHG. The acceptable range for charge current is 300 mA to 3000 mA.
ILIM 8 AI ILIM sets the input current limit. A resistor is connected from ILIM pin to ground to set the input current limit as IINDPM = KILIM/RILIM. The acceptable range for ILIM current is 500 mA to 3200 mA.
The resistor based input current limit is effective only when the input adapter is detected as unknown. Otherwise, the input current limit is determined by D+/D– detection outcome.
OTG 6 DI Boost mode enable pin. When this pin is pulled HIGH, OTG is enabled. OTG cannot be floating.
PG 7 DO Open drain active low power good indicator. Connect to the pull up rail through a 10-kΩ resistor. LOW indicates a good input if the input voltage is between UVLO and ACOV, above SLEEP mode threshold, and input current limit is above 30 mA.
PMID 23 P Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Connect a 10-μF ceramic capacitor between PMID and GND.
REGN 22 P PWM low side driver positive supply output. Internally, REGN is connected to the anode of the boost-strap diode. Connect a 4.7-μF (10-V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close to the IC.
STAT 5 DO Open-drain interrupt output. Connect the STAT pin to a logic rail via 10-kΩ resistor. The STAT pin indicates charger status.
Charge in progress: LOW
Charge complete or charger in SLEEP mode: HIGH
Charge suspend (fault response): Blink at 1 Hz.
SW 19 P Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect a 0.047-μF bootstrap capacitor from SW to BTST.
20
SYS 15 P Converter output connection point. The internal current sensing resistor is connected between SYS and BAT. Connect a 20-µF capacitor close to the SYS pin.
16
TS 11 AI Temperature qualification voltage input to support JEITA profile. Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends when TS pin voltage is out of range. Recommend 103AT-2 thermistor.
VAC 1 AI Input voltage sensing. This pin must be shorted to the VBUS pin.
VBUS 24 P Charger input voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1-uF ceramic capacitor from VBUS to GND and place it as close as possible to the IC.
VSET 12 AI VSET pin sets default battery charge voltage in the BQ25606. Program battery regulation voltage with a resistor pull-down from VSET to GND.
RPD > 50 kΩ (float pin) = 4.208 V
RPD < 500 Ω (short to GND) = 4.352 V
5 kΩ < RPD < 25 kΩ = 4.400 V
Thermal Pad P Ground reference for the device that is also the thermal pad used to conduct heat from the device. This connection serves two purposes. The first purpose is to provide an electrical ground connection for the device. The second purpose is to provide a low thermal-impedance path from the device die to the PCB. This pad should be tied externally to a ground plane.