SLUSDF8E June   2019  – July 2024 BQ25618 , BQ25619

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-On-Reset (POR)
      2. 7.3.2  Device Power Up From Battery Without Input Source
      3. 7.3.3  Power Up From Input Source
        1. 7.3.3.1 Power Up REGN LDO
        2. 7.3.3.2 Poor Source Qualification
        3. 7.3.3.3 Input Source Type Detection (IINDPM Threshold)
          1. 7.3.3.3.1 PSEL Pins Sets Input Current Limit
        4. 7.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 7.3.3.5 Power Up Converter in Buck Mode
        6. 7.3.3.6 HIZ Mode with Adapter Present
      4. 7.3.4  Boost Mode Operation From Battery
      5. 7.3.5  Power Path Management
        1. 7.3.5.1 Narrow VDC Architecture
        2. 7.3.5.2 Dynamic Power Management
        3. 7.3.5.3 Supplement Mode
      6. 7.3.6  Battery Charging Management
        1. 7.3.6.1 Autonomous Charging Cycle
        2. 7.3.6.2 Battery Charging Profile
        3. 7.3.6.3 Charging Termination
        4. 7.3.6.4 Thermistor Qualification
          1. 7.3.6.4.1 JEITA Guideline Compliance During Charging Mode
          2. 7.3.6.4.2 Boost Mode Thermistor Monitor During Battery Discharge Mode
        5. 7.3.6.5 Charging Safety Timer
      7. 7.3.7  Ship Mode and QON Pin
        1. 7.3.7.1 BATFET Disable (Enter Ship Mode)
        2. 7.3.7.2 BATFET Enable (Exit Ship Mode)
        3. 7.3.7.3 BATFET Full System Reset
      8. 7.3.8  Status Outputs (STAT, INT , PMID_GOOD)
        1. 7.3.8.1 Power Good Indicator (PG_STAT Bit)
        2. 7.3.8.2 Charging Status Indicator (STAT)
        3. 7.3.8.3 Interrupt to Host (INT)
        4. 7.3.8.4 PMID Voltage Indicator (PMID_GOOD)
      9. 7.3.9  Protections
        1. 7.3.9.1 Voltage and Current Monitoring in Buck Mode
          1. 7.3.9.1.1 Input Overvoltage Protection (ACOV)
          2. 7.3.9.1.2 System Overvoltage Protection (SYSOVP)
        2. 7.3.9.2 Voltage and Current Monitoring in Boost Mode
          1. 7.3.9.2.1 Boost Mode Overvoltage Protection
          2. 7.3.9.2.2 PMID Overcurrent Protection
        3. 7.3.9.3 Thermal Regulation and Thermal Shutdown
          1. 7.3.9.3.1 Thermal Protection in Buck Mode
          2. 7.3.9.3.2 Thermal Protection in Boost Mode
        4. 7.3.9.4 Battery Protection
          1. 7.3.9.4.1 Battery Overvoltage Protection (BATOVP)
          2. 7.3.9.4.2 Battery Overdischarge Protection
          3. 7.3.9.4.3 System Overcurrent Protection
      10. 7.3.10 Serial Interface
        1. 7.3.10.1 Data Validity
        2. 7.3.10.2 START and STOP Conditions
        3. 7.3.10.3 Byte Format
        4. 7.3.10.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 7.3.10.5 Slave Address and Data Direction Bit
        6. 7.3.10.6 Single Read and Write
        7. 7.3.10.7 Multi-Read and Multi-Write
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host Mode and Default Mode
    5. 7.5 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 Input Capacitor and Resistor
        3. 8.2.2.3 Output Capacitor
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

BQ25618 BQ25619 BQ25618 YFF Package30-Pin WCSPTop View Figure 5-1 BQ25618 YFF Package30-Pin WCSPTop View
BQ25618 BQ25619 BQ25619 RTW Package24-Pin WQFNTop View Figure 5-2 BQ25619 RTW Package24-Pin WQFNTop View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME BQ25618 NO. BQ25619 NO.
BAT C1, D1, E1, F1 13 P Battery connection point to the positive terminal of the battery pack. The internal current sensing resistor is connected between SYS and BAT. Connect a 10 µF closely to the BAT pin.
14
BATSNS F3 10 AIO Battery voltage sensing pin for charge voltage regulation. In order to minimize the parasitic trace resistance during charging, BATSNS pin is connected to the positive terminal of battery pack as close as possible. If BATSNS pin is open or short to ground, BATSNS_STAT bit is set to 1 and charger regulates the battery voltage through BAT pin.
BTST C3 21 P PWM high-side driver positive supply. Internally, the BTST is connected to the cathode of the boot-strap diode. Connect the 0.047-μF bootstrap capacitor from SW to BTST.
CE E3 9 DI Charge enable pin. When this pin is driven LOW, battery charging is enabled.
GND A1, B1 17 P Ground
18
INT F4 7 DO Open-drain interrupt output. Connect the INT to a logic rail through a 10-kΩ resistor. The INT pin sends an active low, 256-µs pulse to the host to report charger device status and fault.
NC B5 8 Not connected
PMID A3, B3 23 DO Boost mode output. Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Consider the total input capacitance, put 1 μF on VBUS to GND, and the rest capacitance on PMID to GND (typical 2x4.7 μF plus 1 nF).
PMID_GOOD D5 3 DO Open drain active high PMID good indicator. Connect to the pullup rail REGN through 10-kΩ resistor. HIGH indicates PMID voltage is below 5.2 V and the current through Q1 is below 110% of input current limit. This signal can be used to drive external PMOS FET to disconnect the PMID under charging load when Boost mode output voltage is too high or output current is too high.
PSEL C5 2 DI Power source selection input. HIGH indicates 500-mA input current limit. LOW indicates 2.4-A input current limit. Once the device gets into Host mode, the host can program a different input current limit to the IINDPM register.
QON D4 12 DI BATFET enable/reset control input. When the BATFET is in Ship mode, a logic LOW of tSHIPMODE duration turns on BATFET to exit Ship mode. When the BATFET is not in Ship mode, a logic LOW of tQON_RST (minimum 8 s) duration resets SYS (system power) by turning BATFET off for tBATFET_RST (minimum 250 ms) and then re-enables BATFET to provide full system power reset. The host chooses the BATFET reset function with VBUS unplug or not through I2C bit BATFET_RST_WVBUS. The pin is pulled up to VBAT through 200 kΩ to maintain default HIGH logic during Ship mode. It has an internal clamp to 6.5 V.
REGN C4 22 P PWM low-side driver positive supply output. Internally, REGN is connected to the anode of the bootstrap diode. Connect a 4.7-μF (10-V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close to the IC.
SCL F5 5 DI I2C interface clock. Connect SCL to the logic rail through a 10-kΩ resistor.
SDA E4 6 DIO I2C interface data. Connect SDA to the logic rail through a 10-kΩ resistor.
STAT E5 4 DO Open-drain interrupt output. Connect the STAT pin to a logic rail via 10-kΩ resistor. The STAT pin indicates charger status.
Charge in progress: LOW
Charge complete or charger in Sleep mode: HIGH
Charge suspend (fault response): Blink at 1 Hz
SW A2, B2 19 P Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047-μF bootstrap capacitor from SW to BTST.
20
SYS C2, D2, E2, F2 15 P Converter output connection point. The internal current sensing resistor is connected between SYS and BAT. Connect a 10 µF (min) closely to the SYS pin.
16
TS D3 11 AI Battery temperature qualification voltage input. Connect a negative temperature coefficient thermistor (NTC). Program temperature window with a resistor divider from REGN to TS to GND. Charge and Boost mode suspend when TS pin voltage is out of range. When TS pin is not used, connect a 10-kΩ resistor from REGN to TS and a 10-kΩ resistor from TS to GND or set TS_IGNORE to HIGH to ignore TS pin. It is recommended to use a 103AT-2 thermistor.
VAC A5 1 AI Input voltage sensing. This pin must be tied to VBUS.
VBUS A4, B4 24 P Charger input voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1-uF ceramic capacitor from VBUS to GND and place it as close as possible to IC.
Thermal Pad — — P Ground reference for the device that is also the thermal pad used to conduct heat from the device. This connection serves two purposes. The first purpose is to provide an electrical ground connection for the device. The second purpose is to provide a low thermal-impedance path from the device die to the PCB. This pad should be tied externally to a ground plane.
(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output, P = Power