SLUSEC9B October 2020 – July 2024 BQ25618E , BQ25619E
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PIN | TYPE(1) | DESCRIPTION | ||
---|---|---|---|---|
NAME | BQ25618E NO. | BQ25619E NO. | ||
BAT | C1, D1, E1, F1 | 13, 14 | P | Battery connection point to the positive terminal of the battery pack. The internal current sensing resistor is connected between SYS and BAT. Connect a 10 µF closely to the BAT pin. |
BATSNS | F3 | 10 | AIO | Battery voltage sensing pin for charge voltage regulation. In order to minimize the parasitic trace resistance during charging, BATSNS pin is connected to the positive terminal of battery pack as close as possible. |
BTST | C3 | 21 | P | PWM high side driver positive supply. Internally, the BTST is connected to the cathode of the boot-strap diode. Connect the 0.047-μF bootstrap capacitor from SW to BTST. |
CE | E3 | 9 | DI | Charge enable pin. When this pin is driven LOW, battery charging is enabled. |
GND | A1, B1 | 17, 18 | P | Ground |
INT | F4 | 7 | DO | Open-drain interrupt output. Connect the INT to a logic rail through a 10-kΩ resistor. The INT pin sends an active low, 256-µs pulse to the host to report charger device status and fault. |
NC | B5, D5 | 8 | — | Not connected. Leave this pin floating. |
PMID | A3, B3 | 23 | DO | Connected to the drain of the reverse-blocking MOSFET (RBFET) and the drain of HSFET. Consider the total input capacitance, put 1 μF on VBUS to GND, and the rest capacitance on PMID to GND (typical 2x4.7 μF plus 1 nF). |
PG | N/A | 3 | DO | Open drain active low power good indicator. Connect to the pull up rail through 10-kΩ resistor. LOW indicates a good input source if the input voltage is between UVLO and ACOV, above SLEEP mode threshold, and current limit is above 30 mA. PG is only for the BQ25619E, not the BQ25618E. |
PSEL | C5 | 2 | DI | Power source selection input. HIGH indicates 500-mA input current limit. LOW indicates 2.4-A input current limit. Once the device gets into host mode, the host can program a different input current limit to the IINDPM register. |
QON | D4 | 12 | DI | BATFET enable/reset control input. When the BATFET is in ship mode, a logic LOW of tSHIPMODE duration turns on BATFET to exit ship mode. When the BATFET is not in ship mode, a logic LOW of tQON_RST (minimum 8 s) duration resets SYS (system power) by turning BATFET off for tBATFET_RST (minimum 250 ms) and then re-enables BATFET to provide full system power reset. The host chooses the BATFET reset function with VBUS unplug or not through I2C bit BATFET_RST_WVBUS. The pin is pulled up to VBAT through 200 kΩ to maintain default HIGH logic during ship mode. It has an internal clamp to 6.5 V. |
REGN | C4 | 22 | P | PWM low side driver positive supply output. Internally, REGN is connected to the anode of the boot-strap diode. Connect a 4.7-μF (10-V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close to the IC. |
SCL | F5 | 5 | DI | I2C interface clock. Connect SCL to the logic rail through a 10-kΩ resistor. |
SDA | E4 | 6 | DIO | I2C interface data. Connect SDA to the logic rail through a 10-kΩ resistor. |
STAT | E5 | 4 | DO | Open-drain interrupt output. Connect the STAT pin to a logic rail
via 10-kΩ resistor. The STAT pin indicates charger status. Charge in progress: LOW Charge complete or charger in SLEEP Mode: HIGH Charge suspend (fault response): Blink at 1 Hz |
SW | A2, B2 | 19, 20 | P | Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047-μF bootstrap capacitor from SW to BTST. |
SYS | C2, D2, E2, F2 | 15, 16 | P | Converter output connection point. The internal current sensing resistor is connected between SYS and BAT. Connect a 10 µF (min) closely to the SYS pin. |
TS | D3 | 11 | AI | Battery temperature qualification voltage input. Connect a negative temperature coefficient thermistor (NTC). Program temperature window with a resistor divider from REGN to TS to GND. Charge suspended when TS pin voltage is out of range. When TS pin is not used, connect a 10-kΩ resistor from REGN to TS and a 10-kΩ resistor from TS to GND or set TS_IGNORE to HIGH to ignore TS pin. It is recommended to use a 103AT-2 thermistor. |
VAC | A5 | 1 | AI | Input voltage sensing. This pin must be tied to VBUS. |
VBUS | A4, B4 | 24 | P | Charger input voltage. The internal n-channel reverse-blocking MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1-μF ceramic capacitor from VBUS to GND and place it as close as possible to IC. |
Thermal Pad | N/A | — | P | Ground reference for the device that is also the thermal pad used to conduct heat from the device. This connection serves two purposes. The first purpose is to provide an electrical ground connection for the device. The second purpose is to provide a low thermal-impedance path from the device die to the PCB. This pad should be tied externally to a ground plane. |