SLUSFA4B June   2023  – February 2024 BQ25628E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-On-Reset (POR)
      2. 8.3.2 Device Power Up from Battery
      3. 8.3.3 Device Power Up from Input Source
        1. 8.3.3.1 REGN LDO Power Up
        2. 8.3.3.2 Poor Source Qualification
        3. 8.3.3.3 ILIM Pin
        4. 8.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 8.3.3.5 Converter Power-Up
      4. 8.3.4 Power Path Management
        1. 8.3.4.1 Narrow VDC Architecture
        2. 8.3.4.2 Dynamic Power Management
        3. 8.3.4.3 High Impedance Mode
      5. 8.3.5 Battery Charging Management
        1. 8.3.5.1 Autonomous Charging Cycle
        2. 8.3.5.2 Battery Charging Profile
        3. 8.3.5.3 Charging Termination
        4. 8.3.5.4 Thermistor Qualification
          1. 8.3.5.4.1 Advanced Temperature Profile in Charge Mode
          2. 8.3.5.4.2 TS Pin Thermistor Configuration
          3. 8.3.5.4.3 JEITA Charge Rate Scaling
          4. 8.3.5.4.4 TS_BIAS Pin
        5. 8.3.5.5 Charging Safety Timers
      6. 8.3.6 Integrated 12-Bit ADC for Monitoring
      7. 8.3.7 Status Outputs ( PG, STAT, INT)
        1. 8.3.7.1 PG Pin Power Good Indicator
        2. 8.3.7.2 Interrupts and Status, Flag and Mask Bits
        3. 8.3.7.3 Charging Status Indicator (STAT)
        4. 8.3.7.4 Interrupt to Host ( INT)
      8. 8.3.8 BATFET Control
        1. 8.3.8.1 Shutdown Mode
        2. 8.3.8.2 Ship Mode
        3. 8.3.8.3 System Power Reset
      9. 8.3.9 Protections
        1. 8.3.9.1 Voltage and Current Monitoring in Battery Only and HIZ Modes
          1. 8.3.9.1.1 Battery Undervoltage Lockout
          2. 8.3.9.1.2 Battery Overcurrent Protection
        2. 8.3.9.2 Voltage and Current Monitoring in Buck Mode
          1. 8.3.9.2.1 Input Overvoltage
          2. 8.3.9.2.2 System Overvoltage Protection (SYSOVP)
          3. 8.3.9.2.3 Forward Converter Cycle-by-Cycle Current Limit
          4. 8.3.9.2.4 System Short
          5. 8.3.9.2.5 Battery Overvoltage Protection (BATOVP)
          6. 8.3.9.2.6 Sleep and Poor Source Comparators
        3. 8.3.9.3 Thermal Regulation and Thermal Shutdown
          1. 8.3.9.3.1 Thermal Protection in Buck Mode
          2. 8.3.9.3.2 Thermal Protection in Battery-Only Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
      2. 8.4.2 Register Bit Reset
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 START and STOP Conditions
        3. 8.5.1.3 Byte Format
        4. 8.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.5.1.5 Target Address and Data Direction Bit
        6. 8.5.1.6 Single Write and Read
        7. 8.5.1.7 Multi-Write and Multi-Read
    6. 8.6 Register Maps
      1. 8.6.1 Register Programming
      2. 8.6.2 BQ25628E Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

13 Revision History

Changes from Revision A (January 2024) to Revision B (February 2024)

  • Added IEC 62368-1 CB CertificationGo
  • Changed TTOP_OFF Typical and Maximum Limit.Go
  • Changed TSAFETY_TRKCHG Typical and Maximum Limit.Go
  • Changed TSAFETY_PRECHG Typical and Maximum Limit.Go
  • Changed TSAFETY Typical and Maximum Limit.Go
  • Changed TBATFET_DLY Typical Value.Go
  • Changed TSM_EXIT Typical and Maximum Limit.Go
  • Changed TQON_RST Typical and Maximum Limit.Go
  • Changed TBATFET_RST Typical Value.Go
  • Changed TLP_WDT Typical Value.Go
  • Changed TWDT Typical Value.Go
  • Changed recommended values of RT1 and RT2 in Section 8.3.5.4.2 Go
  • Added I2C timing requirements for fast mode and fast mode plus in Section 8.5.1.Go
  • Changed TOPOFF_TMR values in Charge_Control_0 Register Description, PRECHG_TMR and CHG_TMR values in Charge_Timer_Control Register Description, and WATCHDOG values in Charger_Control_1 Register Description.Go
  • Updated behavior of IBAT_ADC in IBAT_ADC Register Description.Go

Changes from Revision * (July 2023) to Revision A (January 2024)

  • Added 5mA to 310mA, 5mA steps to Charge termination featureGo
  • Changed tRST to tQON_RST in QON pin descriptionGo
  • Added PG pin descriptionGo
  • Added Maximum limit to VPOORSRC Go
  • Changed IBAT_ADC LSB from 2mA to 4mAGo
  • Removed typical specs for tVBUS_OVP_PROP, TPOORSRC_RETRY, tPOORSRC_RESTART, tVBUS_PD, tTERM_DGL, tRECHG_DGL Go
  • Clarified register conditions for TTOP_OFF specifications.Go
  • Added Figure 8-3 to TS Pin Thermistor ConfigurationGo
  • Updated behavior of battery overcurrent protection in Section 8.3.9.1.2 Go
  • Deleted invalid reference in Section 8.3.9.2.1 to improve clarityGo
  • Deleted invalid reference in Section 8.3.9.2.2 to improve clarityGo
  • Deleted invalid reference in Section 8.3.9.2.4 to improve clarityGo
  • Deleted invalid reference in Section 8.3.9.2.5 to improve clarityGo
  • Deleted invalid reference in Section 8.3.9.2.6 to improve clarityGo
  • Added I2C address in Section 8.5.1.Go
  • Changed bit 5 to Reserved, ICHG Reset from X to Dh, POR from 1Ah to Dh, Range from 2h-4Ch to 1h-26h, and Bit Step from 2h to 1h in Register Fields and Descriptions for REG0x02_Charge_Current_Limit registerGo
  • Changed bit 3 to Reserved, IPRECHG Reset from 0xA to 5h, POR from Ah to 5h, Range from 2h-3Eh to 1h-1Fh, and Bit Step from 2h to 1h in Register Fields and Descriptions for REG0x10_Pre-charge_Control registerGo
  • Changed bit 2 to Reserved, ITERM Reset from 0xC to 6h, POR from Ch to 6h, Range from 2h-7Ch to 1h-3Eh, and Bit Step from 2h to 1h in Register Fields and Descriptions for REG0x12_Termination_Control register Go
  • Changed I2C address from 0x6B to 0x6A in Register Maps section.Go