SLUSFA4B June   2023  – February 2024 BQ25628E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-On-Reset (POR)
      2. 8.3.2 Device Power Up from Battery
      3. 8.3.3 Device Power Up from Input Source
        1. 8.3.3.1 REGN LDO Power Up
        2. 8.3.3.2 Poor Source Qualification
        3. 8.3.3.3 ILIM Pin
        4. 8.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 8.3.3.5 Converter Power-Up
      4. 8.3.4 Power Path Management
        1. 8.3.4.1 Narrow VDC Architecture
        2. 8.3.4.2 Dynamic Power Management
        3. 8.3.4.3 High Impedance Mode
      5. 8.3.5 Battery Charging Management
        1. 8.3.5.1 Autonomous Charging Cycle
        2. 8.3.5.2 Battery Charging Profile
        3. 8.3.5.3 Charging Termination
        4. 8.3.5.4 Thermistor Qualification
          1. 8.3.5.4.1 Advanced Temperature Profile in Charge Mode
          2. 8.3.5.4.2 TS Pin Thermistor Configuration
          3. 8.3.5.4.3 JEITA Charge Rate Scaling
          4. 8.3.5.4.4 TS_BIAS Pin
        5. 8.3.5.5 Charging Safety Timers
      6. 8.3.6 Integrated 12-Bit ADC for Monitoring
      7. 8.3.7 Status Outputs ( PG, STAT, INT)
        1. 8.3.7.1 PG Pin Power Good Indicator
        2. 8.3.7.2 Interrupts and Status, Flag and Mask Bits
        3. 8.3.7.3 Charging Status Indicator (STAT)
        4. 8.3.7.4 Interrupt to Host ( INT)
      8. 8.3.8 BATFET Control
        1. 8.3.8.1 Shutdown Mode
        2. 8.3.8.2 Ship Mode
        3. 8.3.8.3 System Power Reset
      9. 8.3.9 Protections
        1. 8.3.9.1 Voltage and Current Monitoring in Battery Only and HIZ Modes
          1. 8.3.9.1.1 Battery Undervoltage Lockout
          2. 8.3.9.1.2 Battery Overcurrent Protection
        2. 8.3.9.2 Voltage and Current Monitoring in Buck Mode
          1. 8.3.9.2.1 Input Overvoltage
          2. 8.3.9.2.2 System Overvoltage Protection (SYSOVP)
          3. 8.3.9.2.3 Forward Converter Cycle-by-Cycle Current Limit
          4. 8.3.9.2.4 System Short
          5. 8.3.9.2.5 Battery Overvoltage Protection (BATOVP)
          6. 8.3.9.2.6 Sleep and Poor Source Comparators
        3. 8.3.9.3 Thermal Regulation and Thermal Shutdown
          1. 8.3.9.3.1 Thermal Protection in Buck Mode
          2. 8.3.9.3.2 Thermal Protection in Battery-Only Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
      2. 8.4.2 Register Bit Reset
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 START and STOP Conditions
        3. 8.5.1.3 Byte Format
        4. 8.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.5.1.5 Target Address and Data Direction Bit
        6. 8.5.1.6 Single Write and Read
        7. 8.5.1.7 Multi-Write and Multi-Read
    6. 8.6 Register Maps
      1. 8.6.1 Register Programming
      2. 8.6.2 BQ25628E Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.6 Integrated 12-Bit ADC for Monitoring

The BQ25628E provides an integrated 12-bit ADC for the host to monitor various system parameters.

To enable the ADC, the ADC_EN bit must be set to ‘1’. The ADC is disabled by default (ADC_EN = 0) to conserve power. The ADC is allowed to operate if either VBUS > VPOORSRC or VBAT > VBAT_LOWV is valid. If ADC_EN is set to ‘1’ before VBUS or VBAT reach their respective valid thresholds, then ADC_EN stays '0'. The host can enable the ADC during HIZ mode by setting ADC_EN = 1.

At battery only condition, if the TS_ADC channel is enabled, the ADC only operates when the battery voltage is higher than 3.2 V (the minimal value to turn on REGN), otherwise, the ADC operates when the battery voltage is higher than VBAT_LOWV.

The ADC_DONE_STAT, ADC_DONE_FLAG bits are set when a conversion is complete in one-shot mode only. During continuous conversion mode, the ADC_DONE_STAT, ADC_DONE_FLAG bits have no meaning and remain at 0. In one-shot mode, the ADC_EN bit is set to 0 at the completion of the conversion, at the same time as the ADC_DONE_FLAG bit is set. In continuous mode, the ADC_EN bit remains at 1 until the user disables the ADC by setting it to 0.