9.2.2.1 ACP-ACN Input Filter

The bq25708 has average current mode control. The input current sensing through ACP/ACN is critical to recover inductor current ripple. Parasitic inductance on board will generate high frequency ringing on ACP-ACN which overwhelms converter sensed inductor current information, so it is difficult to manage parasitic inductance created based on different PCB layout. Bigger parasitic inductance will generate bigger sense current ringing which will cause the average current control loop to go into oscillation.

For real system board condition, we suggest to use below circuit design to get best result and filter noise induced from different PCB parasitic factor. With time constant of filter from 47nsec to 200nsec, the filtering on ringing is effective and in the meantime, the delay of on the sensed signal is small and therefore poses no concern for average current mode control.

Figure 35. ACN-ACP Input Filter

9.2.2.2 Inductor Selection

The bq25708 has two selectable fixed switching frequency. Higher switching frequency allows the use of smaller inductor and capacitor values. Inductor saturation current should be higher than the charging current (I_CHG) plus half the ripple current (I_RIPPLE):

Equation 3.

The inductor ripple current in buck operation depends on input voltage (V_IN), duty cycle (D_BUCK = V_OUT/V_IN), switching frequency (f_S) and inductance (L):

Equation 4.

During boost operation, the duty cycle is:

D_BOOST = 1 – (V_BAT/V_IN)

I_{RIPPLE_BOOST} = D_BOOST x f_S x VBAT/L_BOOST

The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging voltage range is from 9 V to 12.6 V for 3-cell battery pack. For 20 V adapter voltage, 10 V battery voltage gives the maximum inductor ripple current. Another example is 4-cell battery, the battery voltage range is from 12 V to 16.8 V, and 12 V battery voltage gives the maximum inductor ripple current.

Usually inductor ripple is designed in the range of (20-40%) maximum charging current as a trade-off between inductor size and efficiency for a practical design.

9.2.2.3 Input Capacitor

Bulk input capacitors should be locate in front of input current sensing resistor. Do not recommend to put bulk input capacitors between input sensing resistor and switching MOSFET. Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case RMS ripple current is half of the charging current when duty cycle is 0.5 in buck mode. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS current occurs where the duty cycle is closest to 50% and can be estimated by Equation 5:

Equation 5.

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage rating of the capacitor must be higher than normal input voltage level. 25 V rating or higher capacitor is preferred for 19-20 V input voltage. Minimum 10uF effective capacitance (7 pcs of 10uF 0805 size capacitor) is suggested for 45 W-65 W adapter.

Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the input capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high input voltages and small capacitor packages. See the manufacturer's datasheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point.

9.2.2.4 Output Capacitor

Output capacitor also should have enough ripple current rating to absorb output switching ripple current. In buck mode the output capacitor RMS current is given:

To get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed between 10 kHz and 20 kHz. The preferred ceramic capacitor is 25V X7R or X5R for output capacitor. Minimum 10uF effective capacitance (7 pcs of 10uF 0805 size capacitor) is suggested to be placed after the Q4 drain, and 50uF effective distributed capacitance on Vsys output. Place minimum 10uF after the charge current sense resistor for best stability.

Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point.

9.2.2.5 Power MOSFETs Selection

Four external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are internally integrated into the IC with 6V of gate drive voltage. 30 V or higher voltage rating MOSFETs are preferred for 19-20 V input voltage.

Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction loss and switching loss. For the top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance, R_DS(ON), and the gate-to-drain charge, Q_GD. For the bottom side MOSFET, FOM is defined as the product of the MOSFET's on-resistance, R_DS(ON), and the total gate charge, Q_G.

The lower the FOM value, the lower the total power loss. Usually lower R_DS(ON) has higher cost with the same package size.

The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle (D=V_OUT/V_IN), charging current (I_CHG), MOSFET's on-resistance (R_DS(ON)), input voltage (V_IN), switching frequency (f_S), turn on time (t_on) and turn off time (t_off):

Equation 7.

The first item represents the conduction loss. Usually MOSFET R_DS(ON) increases by 50% with 100°C junction temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn-off times are given by:

Equation 8.

where Q_sw is the switching charge, I_on is the turn-on gate driving current and I_off is the turn-off gate driving current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge (Q_GD) and gate-to-source charge (Q_GS):

Equation 9.

Gate driving current can be estimated by REGN voltage (V_REGN), MOSFET plateau voltage (V_plt), total turn-on gate resistance (R_on) and turn-off gate resistance (R_off) of the gate driver:

Equation 10.

The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in synchronous continuous conduction mode:

When charger operates in non-synchronous mode, the bottom-side MOSFET is off. As a result all the freewheeling current goes through the body-diode of the bottom-side MOSFET. The body diode power loss depends on its forward voltage drop (V_F), non-synchronous mode charging current (I_NONSYNC), and duty cycle (D).

The maximum charging current in non-synchronous mode can be up to 0.25 A for a 10 mΩ charging current sensing resistor or 0.5 A if battery voltage is below 2.5 V. The minimum duty cycle happens at lowest battery voltage. Choose the bottom-side MOSFET with either an internal Schottky or body diode capable of carrying the maximum non-synchronous mode charging current.