SLUSCU2 November   2017

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-Up from Battery Without DC Source
      2. 8.3.2 Power-Up From DC Source
        1. 8.3.2.1 CHRG_OK Indicator
        2. 8.3.2.2 Input Voltage and Current Limit Setup
        3. 8.3.2.3 Battery Cell Configuration
        4. 8.3.2.4 Device Hi-Z State
      3. 8.3.3 Converter Operation
        1. 8.3.3.1 Inductor Setting through IADPT Pin
        2. 8.3.3.2 Continuous Conduction Mode (CCM)
        3. 8.3.3.3 Pulse Frequency Modulation (PFM)
      4. 8.3.4 Current and Power Monitor
        1. 8.3.4.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 8.3.4.2 High-Accuracy Power Sense Amplifier (PSYS)
      5. 8.3.5 Input Source Dynamic Power Manage
      6. 8.3.6 Two-Level Adapter Current Limit (Peak Power Mode)
      7. 8.3.7 Processor Hot Indication
        1. 8.3.7.1 PROCHOT During Low Power Mode
        2. 8.3.7.2 PROCHOT Status
      8. 8.3.8 Device Protection
        1. 8.3.8.1 Watchdog Timer
        2. 8.3.8.2 Input Overvoltage Protection (ACOV)
        3. 8.3.8.3 Input Overcurrent Protection (ACOC)
        4. 8.3.8.4 System Overvoltage Protection (SYSOVP)
        5. 8.3.8.5 Battery Overvoltage Protection (BATOVP)
        6. 8.3.8.6 Battery Short
        7. 8.3.8.7 Thermal Shutdown (TSHUT)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forward Mode
        1. 8.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 8.4.1.2 Battery Charging
    5. 8.5 Programming
      1. 8.5.1 SMBus Interface
        1. 8.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 8.5.1.2 Timing Diagrams
    6. 8.6 Register Map
      1. 8.6.1  Setting Charge and PROCHOT Options
        1. 8.6.1.1 ChargeOption0 Register (SMBus address = 12h) [reset = E20Eh]
        2. 8.6.1.2 ChargeOption1 Register (SMBus address = 30h) [reset = 211h]
        3. 8.6.1.3 ChargeOption2 Register (SMBus address = 31h) [reset = 2B7]
        4. 8.6.1.4 ChargeOption3 Register (SMBus address = 32h) [reset = 0h]
        5. 8.6.1.5 ProchotOption0 Register (SMBus address = 33h) [reset = 04A54h]
        6. 8.6.1.6 ProchotOption1 Register (SMBus address = 34h) [reset = 8120h]
        7. 8.6.1.7 ADCOption Register (SMBus address = 35h) [reset = 2000h]
      2. 8.6.2  Charge and PROCHOT Status
        1. 8.6.2.1 ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
        2. 8.6.2.2 ProchotStatus Register (SMBus address = 21h) [reset = 0h]
      3. 8.6.3  ChargeCurrent Register (SMBus address = 14h) [reset = 0h]
        1. 8.6.3.1 Battery Pre-Charge Current Clamp
      4. 8.6.4  MaxChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting]
      5. 8.6.5  MinSystemVoltage Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
        1. 8.6.5.1 System Voltage Regulation
      6. 8.6.6  Input Current and Input Voltage Registers for Dynamic Power Management
        1. 8.6.6.1 Input Current Registers
          1. 8.6.6.1.1 IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4000h]
          2. 8.6.6.1.2 IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) [reset = 0h]
          3. 8.6.6.1.3 InputVoltage Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
      7. 8.6.7  ADCVBUS/PSYS Register (SMBus address = 23h)
      8. 8.6.8  ADCIBAT Register (SMBus address = 24h)
      9. 8.6.9  ADCIINCMPIN Register (SMBus address = 25h)
      10. 8.6.10 ADCVSYSVBAT Register (SMBus address = 26h) (reset = )
      11. 8.6.11 ID Registers
        1. 8.6.11.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h]
        2. 8.6.11.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 0h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 ACP-ACN Input Filter
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Input Capacitor
        4. 9.2.2.4 Output Capacitor
        5. 9.2.2.5 Power MOSFETs Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Layout Consideration of Current Path
      2. 11.2.2 Layout Consideration of Short Circuit Protection
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The bq25708 is a buck boost NVDC (narrow voltage DC) charge controller for multi-chemistry portable applications such as notebook, detachable, ultrabook, tablet and other mobile devices with rechargeable batteries. It provides seamless transition between converter operation modes (buck, boost, or buck boost), fast transient response, and high light load efficiency.

The bq25708 supports wide range of power sources, including USB PD ports, legacy USB ports, traditional ACDC adapters, etc. It takes input voltage from 3.5 V to 24 V, and charges battery of 1-4 series.

The bq25708 features Dynamic Power Management (DPM) to limit the input power and avoid AC adapter overloading. During battery charging, as the system power increases, the charging current will reduce to maintain total input current below adapter rating. If system power demand temporarily exceeds adapter rating, the bq25708 supports NVDC architecture to allow battery discharge energy to supplement system power. For details, refer to System Voltage Regulation section.

In order to be compliant with an Intel IMVP8 compliant system, the bq25708 includes PSYS function to monitor the total platform power from adapter and battery. Besides PSYS, it provides both an independent input current buffer (IADPT) and a battery current buffer (IBAT) with highly accurate current sense amplifiers. If the platform power exceeds the available power from adapter and battery, a PROCHOT signal is asserted to CPU so that the CPU optimizes its performance to the power available to the system.

The bq25708 controls input current, charge current and charge voltage registers with high resolution, high accuracy regulation limits. It also sets the PROCHOT timing and threshold profile to meet system requirements.

8.2 Functional Block Diagram

bq25708 FBD_SLUSCU2.gif

8.3 Feature Description

8.3.1 Power-Up from Battery Without DC Source

If only battery is present and the voltage is above VVBAT_UVLOZ, the BATFET turns on and connects battery to system. By default, the charger is in low power mode (REG0x12[15] = 1) with lowest quiescent current. The LDO stays off. When device moves to performance mode (REG0x12[15] = 0), The host enables IBAT buffer through SMBus to monitor discharge current. For PSYS, PROCHOT or independent comparator, REGN LDO is enabled for an accurate reference.

8.3.2 Power-Up From DC Source

When an input source plugs in, the charger checks the input source voltage to turn on LDO and all the bias circuits. It sets the input current limit before the converter starts.

The power-up sequence from DC source is as follows:

  1. 50 ms after VBUS above VVBUS_CONVEN, enable 6V LDO and CHRG_OK goes HIGH
  2. Input voltage and current limit setup
  3. Battery CELL configuration
  4. 150 ms after VBUS above VVBUS_CONVEN, converter powers up.

8.3.2.1 CHRG_OK Indicator

CHRG_OK is an active HIGH open drain indicator. It indicates the charger is in normal operation when the following conditions are valid:

  • VBUS is above VVBUS_CONVEN
  • VBUS is below VACOV
  • No MOSFET/inductor fault

8.3.2.2 Input Voltage and Current Limit Setup

When CHRG_OK goes LOW, the charger sets default input current limit in REG0x3F() to 3.30A. The actual input current limit is the lower setting of REG0x3F() and ILIM_HIZ pin.

Charger initiates a VBUS voltage measurement without any load (VBUS at no load condition). The default VINDPM threshold is VBUS@noLoad-1.28 V.

After input current and voltage limits are set, the charger device is ready to power up. The host can always update input current and voltage limit based on input source type.

8.3.2.3 Battery Cell Configuration

CELL_BATPRESZ pin is biased with resistors from REGN to CELL_BATPRESZ to GND. After VDDA LDO is activated, the device detects the battery configuration through CELL_BATPRESZ pin bias voltage. Refer to Electrical Characteristics for CELL setting thresholds.

Table 1. Battery Cell Configuration

CELL COUNT PIN VOLTAGE w.r.t. VDDA BATTERY VOLTAGE (REG0x15) SYSOVP
4S 75% 16.800V 19.5V
3S 55% 12.592V 19.5V
2S 40% 8.400V 12V
1S 25% 4.192V 5V

8.3.2.4 Device Hi-Z State

The charger enters Hi-Z mode when ILIM_HIZ pin voltage is below 0.4 V or REG0x32[15] is set to 1. During Hi-Z mode, the input source is present, and the charger is in the low quiescent current mode with REGN LDO enabled.

8.3.3 Converter Operation

The charger employs a synchronous buck-boost converter that allows charging from a standard 5-V or a high-voltage power source. The charger operates in buck, buck-boost and boost mode. The buck-boost can operate uninterruptedly and continuously across the three operation modes.

Table 2. MOSFET Operation

MODE BUCK BUCK-BOOST BOOST
Q1 Switching Switching ON
Q2 Switching Switching OFF
Q3 OFF Switching Switching
Q4 ON Switching Switching

8.3.3.1 Inductor Setting through IADPT Pin

The charger reads the inductor value through the IADPT pin.

Table 3. Inductor Setting on IADPT Pin

INDUCTOR IN USE RESISTOR ON IADPT PIN
1 µH 93 kΩ
2.2 µH 137 kΩ
3.3 µH 169 kΩ

8.3.3.2 Continuous Conduction Mode (CCM)

With sufficient charge current, the inductor current does not cross 0 A, which is defined as CCM. The controller starts a new cycle with ramp coming up from 200 mV. As long as error amplifier output voltage is above the ramp voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage exceeds error amplifier output voltage, HSFET turns off and low-side MOSFET (LSFET) turns on. At the end of the cycle, ramp gets reset and LSFET turns off, ready for the next cycle. There is always break-before-make logic during transition to prevent cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the body-diode of the low-side power MOSFET conducts the inductor current.

During CCM, the inductor current always flows and creates a fixed two-pole system. Having the LSFET turn-on when the HSFET is off, keeps the power dissipation low and allows safe charging at high currents.

8.3.3.3 Pulse Frequency Modulation (PFM)

In order to improve converter light-load efficiency, the bq25708 switches to PFM control at light load condition. The effective switching frequency will decrease accordingly when system load decreases. The minimum frequency can be limit to 25kHz (ChargeOption0() bit[10]=1).

8.3.4 Current and Power Monitor

8.3.4.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)

As an industry standard, a high-accuracy current sense amplifier (CSA) is used to monitor the input current during forward charging, and the charge/discharge current (IBAT). IADPT voltage is 20× or 40× the differential voltage across ACP and ACN. IBAT voltage is 8x/16× (during charging), or 8×/16× (during discharging) of the differential across SRP and SRN. After input voltage or battery voltage is above UVLO, IADPT output becomes valid. To lower the voltage on current monitoring, a resistor divider from CSA output to GND can be used and accuracy over temperature can still be achieved.

  • V(IADPT) = 20 or 40 × (V(ACP) – V(ACN)) during forward mode.
  • V(IBAT) = 8 or 16 × (V(SRP) – V(SRN)) during forward charging mode.
  • V(IBAT) = 8 or 16 × (V(SRN) – V(SRP)) during forward supplement mode.

A maximum 100-pF capacitor is recommended to connect on the output for decoupling high-frequency noise. An additional RC filter is optional, if additional filtering is desired. Note that adding filtering also adds additional response delay. The CSA output voltage is clamped at 3.3 V.

8.3.4.2 High-Accuracy Power Sense Amplifier (PSYS)

The charger monitors total system power. During forward mode, the input adapter powers system. The ratio of PSYS current and total power KPSYS can be programmed in REG0x30[9] with default 1 μA/W. The input and charge sense resistors (RAC and RSR) are programmed in REG0x30[11:10]. PSYS voltage can be calculated with Equation 1 where IIN>0 when adapter is in forward charging, and IBAT>0 when the battery is in discharge when the battery is in discharge.

Equation 1. bq25708 eq1_SLUSCK9.gif

For proper PSYS functionality, RAC and RSR values are limited to 10mΩ and 20mΩ.

8.3.5 Input Source Dynamic Power Manage

Refer to Input Current and Input Voltage Registers for Dynamic Power Management.

8.3.6 Two-Level Adapter Current Limit (Peak Power Mode)

Usually adapter can supply current higher than DC rating for a few milliseconds to tens of milliseconds. The charger employs two-level input current limit, or peak power mode, to fully utilize the overloading capability and minimize battery discharge during CPU turbo mode. Peak power mode is enabled in REG0x31[13] (EN_PKPWR_IDPM) or REG0x31[12] (EN_PKPWR_VSYS). The DC current limit, or ILIM1, is the same as adapter DC current, set in REG0x3F(). The overloading current, or ILIM2, is set in REG0x33[15:11], as a percentage of ILIM1.

When the charger detects input current surge and battery discharge due to load transient, it applies ILIM2 for TOVLD in REG0x31[15:14], first, and then ILIM1 for up to TMAX – TOVLD time. TMAX is programmed in REG0x31[9:8]. After TMAX, if the load is still high, another peak power cycle starts. Charging is disabled during TMAX,; once TMAX, expires, charging continues. If TOVLD is programmed higher than TMAX, then peak power mode is always on.

bq25708 Two_Level_SLUSCK9.gif Figure 8. Two-Level Adapter Current Limit Timing Diagram

8.3.7 Processor Hot Indication

When CPU is running turbo mode, the system peak power may exceed available power from adapter and battery together. The adapter current and battery discharge peak current, or system voltage drop is an indication that system power is too high. The charger processor hot function monitors these events, and PROCHOT pulse is asserted. Once CPU receives PROCHOT pulse from charger, it slows down to reduce the system power. The processor hot function monitors these events, and PROCHOT pulse is asserted.

The PROCHOT triggering events include:

  • ICRIT: adapter peak current, as 110% of ILIM2
  • INOM: adapter average current (110% of input current limit)
  • IDCHG: battery discharge current
  • VSYS: system voltage on VSYS
  • Adapter Removal: upon adapter removal (CHRG_OK pin HIGH to LOW)
  • Battery Removal: upon battery removal (CELL_BATPRESZ pin goes LOW)
  • CMPOUT: Independent comparator output (CMPOUT pin HIGH to LOW)

The threshold of ICRIT, IDCHG or VSYS, and the deglitch time of ICRIT, INOM, IDCHG or CMPOUT are programmable through SMBus. Each triggering event can be individually enabled in REG0x34[6:0]. When any event in PROCHOT profile is triggered, PROCHOT is asserted low for minimum 10 ms programmable in 0x33[4:3]. At the end of the 10 ms, if the PROCHOT event is still active, the pulse gets extended.

bq25708 prochot_profile_SLUSCK9.gif Figure 9. PROCHOT Profile

8.3.7.1 PROCHOT During Low Power Mode

During low power mode (REG0x12[15]=1), the charger offers a low quiescent current (~150 uA) Low power PROCHOT function uses the independent comparator to monitor battery discharge current and system voltage, and assert PROCHOT to CPU.

Below lists the register setting to enable PROCHOT during low power mode.

  • REG0x12[15]=1
  • REG0x34[5:0]=000000
  • REG0x30[6:4]=100
  • Independent comparator threshold is always 1.2V
  • When REG0x30[14]=1, charger monitors discharge current. Connect CMPIN to voltage proportional to IBAT pin. PROCHOT triggers from HIGH to LOW when CMPIN voltage falls below 1.2V.
  • When REG0x30[13]=1, charger monitors system voltage. Connect CMPIN to voltage proportional to system. PROCHOT triggers from HIGH to LOW when CMPIN voltage rises above 1.2V.
bq25708 Low_Power_PROCHOT_BD_sluscu2.gif Figure 10. PROCHOT Low Power Mode Implementation

8.3.7.2 PROCHOT Status

REG0x21[6:0] reports which event in the profile triggers PROCHOT by setting the corresponding bit to 1. The status bit can be reset back to 0 after it is read by host, and current PROCHOT event is no longer active.

Assume there are two PROCHOT events, event A and event B. Event A triggers PROCHOT first, but event B is also active. Both status bits will be HIGH. At the end of the 10ms PROCHOT pulse, if PROCHOT is still active (either by A or B), the PROCHOT pulse is extended.

8.3.8 Device Protection

8.3.8.1 Watchdog Timer

The charger includes watchdog timer to terminate charging if the charger does not receive a write MaxChargeVoltage() or write ChargeCurrent() command within 175 s (adjustable via REG0x12[14:13]). When watchdog timeout occurs, all register values are kept unchanged except ChargeCurrent() resets to zero. Battery charging is suspended. Write MaxChargeVoltage() or write ChargeCurrent() commands must be re-sent to reset watchdog timer and resume charging. Writing REG0x12[14:13] = 00 to disable watchdog timer also resumes charging.

8.3.8.2 Input Overvoltage Protection (ACOV)

The charger has fixed ACOV voltage. When VBUS pin voltage is higher than ACOV, it is considered as adapter over voltage. CHRG_OK will be pulled low, and converter will be disabled. As system falls below battery voltage, BATFET will be turned on. When VBUS pin voltage falls below ACOV, it is considered as adapter voltage returns back to normal voltage. CHRG_OK will be pulled high by external pull up resistor. The converter will resume if enable conditions are valid.

8.3.8.3 Input Overcurrent Protection (ACOC)

If the input current exceeds the 1.25× or 2× (REG0x31[2]) of ILIM2_VTH (REG0x33[15:11]) set point, converter stops switching. After 300 ms, converter will start switching again.

8.3.8.4 System Overvoltage Protection (SYSOVP)

When the converter starts up, the bq25708 reads CELL pin configuration and sets MaxChargeVoltage() and SYSOVP threshold (1s – 5 V, 2s – 12 V, 3s/4s – 19.5 V). Before REGx15() is written by host, the battery configuration will change with CELL pin voltage. When SYSOVP happens, the device latches off the converter. REG20[4] is set as 1. The user can clear the latch-off by either writing 0 to SYSOVP bit or removing and plugging in adapter again. After the latch-off is cleared, converter starts again.

8.3.8.5 Battery Overvoltage Protection (BATOVP)

Battery over-voltage may happen when battery is removed during charging or the user plugs in a wrong battery. The BATOVP threshold is 104% (1 s) or 102% (2 s to 4 s) of regulation voltage set in REG0x15().

8.3.8.6 Battery Short

If BAT voltage falls below SYSMIN during charging, the maximum current is limited to 384 mA.

8.3.8.7 Thermal Shutdown (TSHUT)

The WQFN package has low thermal impedance, which provides good thermal conduction from the silicon to the ambient, to keep junction temperatures low. As added level of protection, the charger converter turns off for self-protection whenever the junction temperature exceeds the 155°C. The charger stays off until the junction temperature falls below 135°C. During thermal shut down, the LDO current limit is reduced to 16 mA and REGN LDO stays off. When the temperature falls below 135°C, charge can be resumed with soft start.

8.4 Device Functional Modes

8.4.1 Forward Mode

When input source is connected to VBUS, bq25708 is in forward mode to regulate system and charge battery.

8.4.1.1 System Voltage Regulation with Narrow VDC Architecture

The bq25708 employs Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by MinSystemVoltage(). Even with a deeply depleted battery, the system is regulated above the minimum system voltage.

When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode).

As the battery voltage rises above the minimum system voltage, BATFET is fully on when charging or in supplement mode and the voltage difference between the system and battery is the VDS of BATFET. System voltage is regulated 160 mV above battery voltage when BATFET is off (no charging or no supplement current).

See System Voltage Regulation for details on system voltage regulation and register programming.

8.4.1.2 Battery Charging

The bq25708 charges 1-4 cell battery in constant current (CC), and constant voltage (CV) mode. Based on CELL_BATPREZ pin setting, the charger sets default battery voltage 4.2V/cell to ChargeVoltage(), or REG0x15(). According to battery capacity, the host programs appropriate charge current to ChargeCurrent(), or REG0x14(). When battery is full or battery is not in good condition to charge, host terminates charge by setting REG0x12[0] to 1, or setting ChargeCurrent() to zero.

See Feature Description for details on register programming.

8.5 Programming

The charger supports battery-charger commands that use either Write-Word or Read-Word protocols, as summarized in SMBus Write-Word and Read-Word Protocols. The SMBUS address is 12h (0001001_X), where X is the read/write bit. The ManufacturerID and DeviceID registers are assigned identify the charger device. The ManufacturerID register command always returns 40h.

8.5.1 SMBus Interface

The bq25700 device operates as a slave, receiving control inputs from the embedded controller host through the SMBus interface. The bq25700 device uses a simplified subset of the commands documented in System Management Bus Specification V1.1, which can be downloaded from www.smbus.org. The bq25700 device uses the SMBus read-word and write-word protocols (shown in Table 4 and Table 5) to communicate with the smart battery. The bq25700 device performs only as a SMBus slave device with address 0b00010010 (0x12H) and does not initiate communication on the bus. In addition, the bq25700 device has two identification registers, a 16-bit device ID register (0xFFH) and a 16-bit manufacturer ID register (0xFEH).

SMBus communication starts when VCC is above V(UVLO).

The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose pullup resistors (10 kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications. Communication starts when the master signals a start condition, which is a high-to-low transition on SDA, while SCL is high. When the master has finished communicating, the master issues a stop condition, which is a low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 11 and Figure 12 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and data bytes are transmitted between the start and stop conditions. The SDA state changes only while SCL is low, except for the start and stop conditions. Data is transmitted in 8-bit bytes and is sampled on the rising edge of SCL. Nine clock cycles are required to transfer each byte in or out of the bq25708 device because either the master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The bq25708 supports the charger commands listed in Table 4.

8.5.1.1 SMBus Write-Word and Read-Word Protocols

Table 4. Write-Word Format

S
(1)(3)		 SLAVE ADDRESS(1) W
(1)(6)		 ACK
(2)(5)		 COMMAND BYTE(1) ACK
(2)(5)		 LOW DATA BYTE(1) ACK
(2)(5)		 HIGH DATA BYTE(1) ACK
(2)(5)		 P
(1)(4)
7 bits 1b 1b 8 bits 1b 8 bits 1b 8 bits 1b
MSB LSB 0 0 MSB LSB 0 MSB LSB 0 MSB LSB 0
(1) Master to slave
(2) Slave to master (shaded gray)
(3) S = Start condition or repeated start condition
(4) P = Stop condition
(5) ACK = Acknowledge (logic-low)
(6) W = Write bit (logic-low)

Table 5. Read-Word Format

S(1)(3) SLAVE ADDRESS(1) W
(1)(7)		 ACK
(2)(5)		 COMMAND BYTE(1) ACK
(2)(5)		 S(1)(3) SLAVE ADDRESS(1) R(1)(8) ACK
(2)(5)		 LOW DATA BYTE(2) ACK
(1)(5)		 HIGH DATA BYTE(2) NACK
(1)(6)		 P
(1)(4)
7 bits 1b 1b 8 bits 1b 7 bits 1b 1b 8 bits 1b 8 bits 1b
MSB LSB 0 0 MSB LSB 0 MSB LSB 1 0 MSB LSB 0 MSB LSB 1
(1) Master to slave
(2) Slave to master (shaded gray)
(3) S = Start condition or repeated start condition
(4) P = Stop condition
(5) ACK = Acknowledge (logic-low)
(6) NACK = Not acknowledge (logic-high)
(7) W = Write bit (logic-low)
(8) R = Read bit (logic-high)

8.5.1.2 Timing Diagrams

bq25708 timing_write_SLUSBW0.gif
A = Start condition H = LSB of data clocked into slave
B = MSB of address clocked into slave I = Slave pulls SMBDATA line low
C = LSB of address clocked into slave J = Acknowledge clocked into master
D = R/W bit clocked into slave K = Acknowledge clock pulse
E = Slave pulls SMBDATA line low L = Stop condition, data executed by slave
F = ACKNOWLEDGE bit clocked into master M = New start condition
G = MSB of data clocked into slave
Figure 11. SMBus Write Timing
bq25708 timing_read_SLUSBW0.gif
A = Start condition G = MSB of data clocked into master
B = MSB of address clocked into slave H = LSB of data clocked into master
C = LSB of address clocked into slave I = Acknowledge clock pulse
D = R/W bit clocked into slave J = Stop condition
E = Slave pulls SMBDATA line low K = New start condition
F = ACKNOWLEDGE bit clocked into master
Figure 12. SMBus Read Timing

8.6 Register Map

Table 6. Charger Command Summary

SMBus ADDR REGISTER NAME TYPE DESCRIPTION LINKS
12h ChargeOption0() R/W Charge Option 0 Go
14h ChargeCurrent() R/W 7-bit charge current setting
LSB 64 mA, Range 8128 mA		 Go
15h MaxChargeVoltage() R/W 11-bit charge voltage setting
LSB 16 mV, Default: 1S-4192mV, 2S-8400mV, 3S-12592mV, 4S-16800mV		 Go
30h ChargeOption1() R/W Charge Option 1 Go
31h ChargeOption2() R/W Charge Option 2 Go
32h ChargeOption3() R/W Charge Option 3 Go
33h ProchotOption0() R/W PROCHOT Option 0 Go
34h ProchotOption1() R/W PROCHOT Option 1 Go
35h ADCOption() R/W ADC Option Go
20h ChargerStatus() R Charger Status Go
21h ProchotStatus() R Prochot Status Go
22h IIN_DPM() R 7-bit input current limit in use
LSB: 50mA, Range: 50mA-6400mA		 Go
23h ADCVBUS/PSYS() R 8-bit digital output of input voltage,
8-bit digital output of system power
PSYS: Full range: 3.06V, LSB: 12mV
VBUS: Full range: 3.2V-19.52V, LSB 64mV 		Go
24h ADCIBAT() R 8-bit digital output of battery charge current,
8-bit digital output of battery discharge current
ICHG: Full range 8.128A, LSB 64mA
IDCHG: Full range: 32.512A, LSB: 256mA 		Go
25h ADCIINCMPIN() R 8-bit digital output of input current,
8-bit digital output of CMPIN voltage
POR State - IIN: Full range: 12.75A, LSB 50mA
CMPIN: Full range 3.06V, LSB: 12mV 		Go
26h ADCVSYSVBAT() R 8-bit digital output of system voltage,
8-bit digital output of battery voltage
VSYS: Full range: 2.88V-19.2V, LSB: 64mV
VBAT: Full range : 2.88V-19.2V, LSB 64mV 		Go
3Bh Reserved R/W
3Ch Reserved R/W
3Dh InputVoltage() R/W 8-bit input voltage setting
LSB 64mV, Range: 3200 mV – 19520 mV		 Go
3Eh MinSystemVoltage() R/W 6-Bit minimum system voltage setting
LSB: 256mV, Range: 1024mV-16182mV
Default: 1S-3.584V, 2S-6.144V, 3S-9.216V, 4S-12.288V		 Go
3Fh IIN_HOST() R/W 6-bit Input current limit set by host
LSB: 50mA, Range: 50mA-6400mA		 Go
FEh ManufacturerID() R Manufacturer ID - 0x0040H Go
FFh DeviceID() R Device ID Go

8.6.1 Setting Charge and PROCHOT Options

8.6.1.1 ChargeOption0 Register (SMBus address = 12h) [reset = E20Eh]

Figure 13. ChargeOption0 Register (SMBus address = 12h) [reset = E20Eh]
15 14 13 12 11 10 9 8
EN_LWPWR WDTMR_ADJ IDPM_AUTO_
DISABLE		 Reserved EN_OOA PWM_FREQ Reserved
R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
Reserved EN_LEARN IADPT_GAIN IBAT_GAIN EN_LDO EN_IDPM CHRG_INHIBIT
R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. ChargeOption0 Register (SMBus address = 12h) Field Descriptions

SMBus
BIT 		FIELD TYPE RESET DESCRIPTION
15 EN_LWPWR R/W 1b

Low Power Mode Enable

0b: Disable Low Power Mode. Device in performance mode with battery only. The PROCHOT, current/power monitor buffer and comparator follow register setting.

1b: Enable Low Power Mode. Device in low power mode with battery only for lowest quiescent current. /PROCHOT, discharge current monitor buffer, power monitor buffer and independent comparator are disabled. Independent comparator can be enabled by setting either REG0X30()[14] or [13] to 1. <default at POR>
14-13 WDTMR_ADJ R/W 11b

WATCHDOG Timer Adjust

Set maximum delay between consecutive SMBus write of charge voltage or charge current command.

If device does not receive a write on the REG0x15() or the REG0x14() within the watchdog time period, the charger will be suspended by setting the REG0x14() to 0 mA.

After expiration, the timer will resume upon the write of REG0x14(), REG0x15() or REG0x12[14:13]. The charger will resume if the values are valid.

00b: Disable Watchdog Timer

01b: Enabled, 5 sec

10b: Enabled, 88 sec

11b: Enable Watchdog Timer, 175 sec <default at POR>
12 IDPM_AUTO_
DISABLE		 R/W 0b

IDPM Auto Disable

When CELL_BATPRESZ pin is LOW, the charger automatically disables the IDPM function by setting EN_IDPM (REG0x12[1]) to 0. The host can enable IDPM function later by writing EN_IDPM bit (REG0x12[1]) to 1.

0b: Disable this function. IDPM is not disabled when CELL_BATPRESZ goes LOW. <default at POR>

1b: Enable this function. IDPM is disabled when CELL_BATPRESZ goes LOW.

11 Reserved R/W Reserved
10 EN_OOA R/W 0b

Out-of-Audio Enable

0b: No limit of PFM burst frequency <default at POR>

1b: Set minimum PFM burst frequency to above 25 kHz to avoid audio noise

9 PWM_FREQ R/W 1b

Switching Frequency

Two converter switching frequencies. One for small inductor and the other for big inductor.

Currently, customer uses 800 kHz with 2.2 µH or 3.3 µH, and 1.2 MHz with 1 µH or 1.5 µH.

0b: 1.2 MHz

1b: 800 kHz <default at POR>
8 Reserved R/W 0b Reserved

Table 8. ChargeOption0 Register (SMBus address = 12h) Field Descriptions

SMBus
BIT 		FIELD TYPE RESET DESCRIPTION
7-6 Reserved R/W 00b Reserved
5 EN_LEARN R/W 0b

LEARN function allows the battery to discharge while the adapter is present. It calibrates the battery gas gauge over a complete discharge/charge cycle. When the battery voltage is below battery depletion threshold, the system switches back to adapter input by the host. When CELL_BATPRESZ pin is LOW, the device exits LEARN mode and this bit is set back to 0.

0b: Disable LEARN Mode <default at POR>

1b: Enable LEARN Mode
4 IADPT_GAIN R/W 0b

IADPT Amplifier Ratio

The ratio of voltage on IADPT and voltage across ACP and ACN.

0b: 20× <default at POR>

1b: 40×

3 IBAT_GAIN R/W 1b

IBAT Amplifier Ratio

The ratio of voltage on IBAT and voltage across SRP and SRN

0b: 8×

1b: 16× <default at POR>
2 EN_LDO R/W 1b

LDO Mode Enable

When battery voltage is below minimum system voltage (REG0x3E()), the charger is in pre-charge with LDO mode enabled.

0b: Disable LDO mode, BATFET fully ON. Precharge current is set by battery pack internal resistor. The system is regulated by the MaxChargeVoltage register.

1b: Enable LDO mode, Precharge current is set by the ChargeCurrent register and clamped below 384 mA (2 cell – 4 cell) or 2A (1 cell). The system is regulated by the MinSystemVoltage register. <default at POR>
1 EN_IDPM R/W 1b

IDPM Enable

Host writes this bit to enable IDPM regulation loop. When the IDPM is disabled by the charger (refer to IDPM_AUTO_DISABLE), this bit goes LOW.

0b: IDPM disabled

1b: IDPM enabled <default at POR>
0 CHRG_INHIBIT R/W 0b

Charge Inhibit

When this bit is 0, battery charging will start with valid values in the MaxChargeVoltage register and the ChargeCurrent register.

0b: Enable Charge <default at POR>

1b: Inhibit Charge

8.6.1.2 ChargeOption1 Register (SMBus address = 30h) [reset = 211h]

Figure 14. ChargeOption1 Register (SMBus address = 30h) [reset = 211h]
15 14 13 12 11 10 9 8
EN_IBAT EN_PROCHOT_LPWR EN_PSYS RSNS_RAC RSNS_RSR PSYS_RATIO Reserved
R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
CMP_REF CMP_POL CMP_DEG FORCE_
LATCHOFF		 Reserved EN_SHIP_
DCHG		 AUTO_
WAKEUP_EN
R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. ChargeOption1 Register (SMBus address = 30h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
15 EN_IBAT R/W 0b

IBAT Enable

Enable the IBAT output buffer. In low power mode (REG0x12[15] = 1), IBAT buffer is always disabled regardless of this bit value.

0b Turn off IBAT buffer to minimize Iq <default at POR>

1b: Turn on IBAT buffer

14-13 EN_PROCHOT
_LPWR 		R/W 00b

Enable PROCHOT during battery only low power mode

With battery only, enable IDCHG or VSYS in PROCHOT with low power consumption. Do not enable this function with adapter present. Refer to PROCHOT During Low Power Mode for more details.

00b: Disable low power PROCHOT <default at POR>

01b: Enable IDCHG low power PROCHOT

10b: Enable VSYS low power PROCHOT

11b: Reserved
12 EN_PSYS R/W 0b

PSYS Enable

Enable PSYS sensing circuit and output buffer (whole PSYS circuit). In low power mode (REG0x12[15] = 1), PSYS sensing and buffer are always disabled regardless of this bit value.

0b: Turn off PSYS buffer to minimize Iq <default at POR>

1b: Turn on PSYS buffer

11 RSNS_RAC R/W 0b

Input sense resistor RAC

0b: 10 mΩ <default at POR>

1b: 20 mΩ
10 RSNS_RSR R/W 0b

Charge sense resistor RSR

0b: 10 mΩ <default at POR>

1b: 20 mΩ
9 PSYS_RATIO R/W 1b

PSYS Gain

Ratio of PSYS output current vs total input and battery power with 10-mΩ sense resistor.

0b: 0.25 µA/W

1b: 1 µA/W <default at POR>
8 Reserved R/W 0b

Reserved

Table 10. ChargeOption1 Register (SMBus address = 30h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
7 CMP_REF R/W 0b

Independent Comparator Internal Reference

0b: 2.3 V <default at POR>

1b: 1.2 V

6 CMP_POL R/W 0b

Independent Comparator Output Polarity

0b: When CMPIN is above internal threshold, CMPOUT is LOW (internal hysteresis) <default at POR>

1b: When CMPIN is below internal threshold, CMPOUT is LOW (external hysteresis)
5-4 CMP_DEG R/W 01b

Independent Comparator Deglitch Time, only applied to the falling edge of CMPOUT (HIGH → LOW).

00b: Independent comparator is disabled

01b: Independent comparator is enabled with output deglitch time 1 µs <default at POR>

10b: Independent comparator is enabled with output deglitch time of 2 ms

11b: Independent comparator is enabled with output deglitch time of 5 sec

3 FORCE_LATCHOFF R/W 0b

Force Power Path Off

When the independent comparator triggers, charger turns off Q1 and Q4 (same as disable converter) so that the system is disconnected from the input source. At the same time, CHRG_OK signal goes to LOW to notify the system.

0b: Disable this function <default at POR>

1b: Enable this function
2 Reserved R/W 0b

Reserved

1 EN_SHIP_DCHG R/W 0b

Discharge SRN for Shipping Mode

When this bit is 1, discharge SRN pin down below 3.8 V in 140 ms. When 140 ms is over, this bit is reset to 0.

0b: Disable shipping mode <default at POR>

1b: Enable shipping mode

0 AUTO_WAKEUP_EN R/W 1b

Auto Wakeup Enable

When this bit is HIGH, if the battery is below minimum system voltage (REG0x3E()), the device will automatically enable 128 mA charging current for 30 mins. When the battery is charged up above minimum system voltage, charge will terminate and the bit is reset to LOW.

0b: Disable

1b: Enable <default at POR>

8.6.1.3 ChargeOption2 Register (SMBus address = 31h) [reset = 2B7]

Figure 15. ChargeOption2 Register (SMBus address = 31h) [reset = 2B7]
15 14 13 12 11 10 9 8
PKPWR_TOVLD_DEG EN_PKPWR
_IDPM		 EN_PKPWR
_VSYS		 PKPWR_
OVLD_STAT		 PKPWR_
RELAX_STAT		 PKPWR_TMAX[1:0]
R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
EN_EXTILIM EN_ICHG
_IDCHG		 Q2_OCP ACX_OCP EN_ACOC ACOC_VTH EN_BATOC BATOC_VTH
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. ChargeOption2 Register (SMBus address = 31h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
15-14 PKPWR_
TOVLD_DEG		 R/W 00b

Input Overload time in Peak Power Mode

00b: 1 ms <default at POR>

01b: 2 ms

10b: 10 ms

11b: 20 ms
13 EN_PKPWR_IDPM R/W 0b

Enable Peak Power Mode triggered by input current overshoot

If REG0x31[13:12] are 00b, peak power mode is disabled. Upon adapter removal, the bits are reset to 00b.

0b: Disable peak power mode triggered by input current overshoot <default at POR>

1b: Enable peak power mode triggered by input current overshoot.
12 EN_PKPWR_VSYS R/W 0b

Enable Peak Power Mode triggered by system voltage under-shoot

If REG0x31[13:12] are 00b, peak power mode is disabled. Upon adapter removal, the bits are reset to 00b.

0b: Disable peak power mode triggered by system voltage under-shoot <default at POR>

1b: Enable peak power mode triggered by system voltage under-shoot.
11 PKPWR_
OVLD_STAT		 R/W 0b

Indicator that the device is in overloading cycle. Write 0 to get out of overloading cycle.

0b: Not in peak power mode. <default at POR>

1b: In peak power mode.

10 PKPWR_
RELAX_STAT		 R/W 0b

Indicator that the device is in relaxation cycle. Write 0 to get out of relaxation cycle.

0b: Not in relaxation cycle. <default at POR>

1b: In relaxation mode.

9-8 PKPWR_
TMAX[1:0]		 R/W 10b

Peak power mode overload and relax cycle time.

When REG0x31[15:14] is programmed longer than REG0x31[9:8], there is no relax time.

00b: 5 ms

01b: 10 ms

10b: 20 ms <default at POR>

11b: 40 ms

Table 12. ChargeOption2 Register (SMBus address = 31h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
7 EN_EXTILIM R/W 1b

Enable ILIM_HIZ pin to set input current limit

0b: Input current limit is set by REG0x3F.

1b: Input current limit is set by the lower value of ILIM_HIZ pin and REG0x3F. <default at POR>
6 EN_ICHG
_IDCHG		 R/W 0b

0b: IBAT pin as discharge current. <default at POR>

1b: IBAT pin as charge current.

5 Q2_OCP R/W 1b

Q2 OCP threshold by sensing Q2 VDS

0b: 300 mV

1b: 500 mV <default at POR>
4 ACX_OCP R/W 1b

Input current OCP threshold by sensing ACP-ACN.

0b: 150 mV

1b: 280 mV <default at POR>
3 EN_ACOC R/W 0b

ACOC Enable

Input overcurrent (ACOC) protection by sensing the voltage across ACP and ACN. Upon ACOC (after 100-µs blank-out time), converter is disabled.

0b: Disable ACOC <default at POR>

1b: ACOC threshold 125% or 200% ICRIT
2 ACOC_VTH R/W 1b

ACOC Limit

Set MOSFET OCP threshold as percentage of IDPM with current sensed from RAC.

0b: 125% of ICRIT

1b: 200% of ICRIT <default at POR>
1 EN_BATOC R/W 1b

BATOC Enable

Battery discharge overcurrent (BATOC) protection by sensing the voltage across SRN and SRP. Upon BATOC, converter is disabled.

0b: Disable BATOC

1b: BATOC threshold 125% or 200% PROCHOT IDCHG <default at POR>
0 BATOC_VTH R/W 1b

Set battery discharge overcurrent threshold as percentage of PROCHOT battery discharge current limit.

0b: 125% of PROCHOT IDCHG

1b: 200% of PROCHOT IDCHG <default at POR>

8.6.1.4 ChargeOption3 Register (SMBus address = 32h) [reset = 0h]

Figure 16. ChargeOption3 Register (SMBus address = 32h) [reset = 0h]
15 14 13 12 11 10 9 8
EN_HIZ RESET_REG RESET_
VINDPM		 Reserved EN_ICO_MODE Reserved
R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
Reserved BATFETOFF_
HIZ		 Reserved
R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. ChargeOption3 Register (SMBus address = 32h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
15 EN_HIZ R/W 0b

Device Hi-Z Mode Enable

When the charger is in Hi-Z mode, the device draws minimal quiescent current. With VBUS above UVLO. REGN LDO stays on, and system powers from battery.

0b: Device not in Hi-Z mode <default at POR>

1b: Device in Hi-Z mode
14 RESET_REG R/W 0b

Reset Registers

All the registers go back to the default setting except the VINDPM

register.

0b: Idle <default at POR>

1b: Reset all the registers to default values. After reset, this bit goes back to 0.

13 RESET_VINDPM R/W 0b

Reset VINDPM Threshold

0b: Idle

1b: Converter is disabled to measure VINDPM threshold. After VINDPM measurement is done, this bit goes back to 0 and converter starts.
12 Reserved R/W Reserved
11 EN_ICO_MODE R/W 0b

Enable ICO Algorithm

0b: Disable ICO algorithm. <default at POR>

1b: Enable ICO algorithm.

10-8 Reserved R/W 000b

Reserved

Table 14. ChargeOption3 Register (SMBus address = 32h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
7-2 Reserved R/W 000000b

Reserved
1 BATFETOFF_
HIZ		 R/W 0b

Control BATFET during HIZ mode.

0b: BATFET on during Hi-Z <default at POR>

1b: BATFET off during Hi-Z
0 Reserved R/W

8.6.1.5 ProchotOption0 Register (SMBus address = 33h) [reset = 04A54h]

Figure 17. ProchotOption0 Register (SMBus address = 33h) [reset = 04A54h]
15-11 10-9 8
ILIM2_VTH ICRIT_DEG Reserved
R/W R/W R/W
7-6 5 4-3 2 1 0
VSYS_VTH EN_PROCHOT_EXT PROCHOT_WIDTH PROCHOT_
CLEAR		 INOM_DEG Reserved
R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. ProchotOption0 Register (SMBus address = 33h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
15-11 ILIM2_VTH R/W 01001b

ILIM2 Threshold

5 bits, percentage of IDPM in 0x3FH. Measure current between ACP and ACN.

Trigger when the current is above this threshold:

00001b - 11001b: 110% - 230%, step 5%

11010b - 11110b: 250% - 450%, step 50%

11111b: Out of Range (Ignored)

Default 150%, or 01001
10-9 ICRIT_DEG R/W 01b

ICRIT Deglitch time

ICRIT threshold is set to be 110% of ILIM2.

Typical ICRIT deglitch time to trigger PROCHOT.

00b: 15 µs

01b: 100 µs <default at POR>

10b: 400 µs (max 500 us)

11b: 800 µs (max 1 ms)
8 Reserved R/W 0b

Reserved

Table 16. ProchotOption0 Register (SMBus address = 33h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
7-6 VSYS_VTH R/W 01b

VSYS Threshold

Measure on VSYS with fixed 20-µs deglitch time. Trigger when SYS pin voltage is below the threshold.

00b: 5.75 V (2-4 s) or 2.85 V (1 s)

01b: 6 V (2-4 s) or 3.1 V (1 s) <default at POR>

10b: 6.25 V (2-4 s) or 3.35 V (1 s)

11b: 6.5 V (2-4 s) or 3.6 V (1 s)

5 EN_PROCHOT
_EXT		 R/W 0b

PROCHOT Pulse Extension Enable

When pulse extension is enabled, keep the PROCHOT pin voltage LOW until host writes 0x33[2] = 0.

0b: Disable pulse extension <default at POR>

1b: Enable pulse extension

4-3 PROCHOT
_WIDTH		 R/W 10b

PROCHOT Pulse Width

Minimum PROCHOT pulse width when REG0x33[5] = 0

00b: 100 µs

01b: 1 ms

10b: 10 ms <default at POR>

11b: 5 ms
2 PROCHOT
_CLEAR		 R/W 1b

PROCHOT Pulse Clear

Clear PROCHOT pulse when 0x3C[5] = 1.

0b: Clear PROCHOT pulse and drive PROCHOT pin HIGH.

1b: Idle <default at POR>
1 INOM_DEG R/W 0b

INOM Deglitch Time

INOM is always 10% above IDPM in 0x3FH. Measure current between ACP and ACN.

Trigger when the current is above this threshold.

0b: 1 ms (must be max) <default at POR>

1b: 50 ms (max 60 ms)
0 Reserved R/W 0b

Reserved

8.6.1.6 ProchotOption1 Register (SMBus address = 34h) [reset = 8120h]

Figure 18. ProchotOption1 Register (SMBus address = 34h) [reset = 8120h]
15-10 9-8
IDCHG_VTH IDCHG_DEG
R/W R/W
7 6 5 4 3 2 1 0
Reserved PROCHOT_PROFILE_IC PP_ICRIT PP_INOM PP_IDCHG PP_VSYS PP_BATPRES PP_ACOK
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. ProchotOption1 Register (SMBus address = 34h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
15-10 IDCHG_VTH R/W 000000b

IDCHG Threshold

6 bit, range, range 0 A to 32256 mA, step 512 mA. There is a 128 mA offset measured current between SRN and SRP.

Trigger when the discharge current is above the threshold.

If the value is programmed to 000000b, PROCHOT is always triggered.

Default: 16384 mA or 100000
9-8 IDCHG_DEG R/W 01b

IDCHG Deglitch Time

00b: 1.6 ms

01b: 100 µs <default at POR>

10b: 6 ms

11b: 12 ms

Table 18. ProchotOption1 Register (SMBus address = 34h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
7 Reserved R/W 0b

Reserved
6 PROCHOT
_PROFILE_COMP		 R/W 0b

PROCHOT Profile

When all the REG0x34[6:0] bits are 0, PROCHOT function is disabled.

Bit6 Independent comparator

0b: disable <default at POR>

1b: enable
5 PROCHOT
_PROFILE_ICRIT		 R/W 1b

0b: disable

1b: enable <default at POR>
4 PROCHOT
_PROFILE_INOM		 R/W 0b

0b: disable <default at POR>

1b: enable
3 PROCHOT
_PROFILE_IDCHG		 R/W 0b

0b: disable <default at POR>

1b: enable

2 PROCHOT
_PROFILE_VSYS		 R/W 0b

0b: disable <default at POR>

1b: enable
1 PROCHOT
_PROFILE_BATPRES		 R/W 0b

0b: disable <default at POR>

1b: enable (one-shot falling edge triggered)

If BATPRES is enabled in PROCHOT after the battery is removed, it will immediately send out one-shot PROCHOT pulse.

0 PROCHOT
_PROFILE_ACOK		 R/W 0b

0b: disable <default at POR>

1b: enable (one-shot falling edge triggered)

ChargeOption0[15] = 0 to pull PROCHOT low after adapter removal.

If BATPRES is enabled in PROCHOT after the battery is removed, it will immediately send out one-shot PROCHOT pulse.

8.6.1.7 ADCOption Register (SMBus address = 35h) [reset = 2000h]

Figure 19. ADCOption Register (SMBus address = 35h) [reset = 2000h]
15 14 13 12-8
ADC_CONV ADC_START ADC_
FULLSCALE		 Reserved
R/W R/W R/W R/W
7 6 5 4 3 2 1 0
EN_ADC_
CMPIN		 EN_ADC_
VBUS 		EN_ADC_
PSYS 		EN_ADC_
IIN 		EN_ADC_
IDCHG 		EN_ADC_
ICHG 		EN_ADC_
VSYS 		EN_ADC_
VBAT
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. ADCOption Register (SMBus address = 35h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
15 ADC_CONV R/W 0b Typical ADC conversion time is 10 ms.
0b: One-shot update. Do one set of conversion updates to registers REG0x23(), REG0x24(), REG0x25(), and REG0x26() after ADC_START = 1.
1b: Continuous update. Do a set of conversion updates to registers REG0x23(), REG0x24(), REG0x25(), and REG0x26() every 1 sec.
14 ADC_START R/W 0b

0b: No ADC conversion

1b: Start ADC conversion. After the one-shot update is complete, this bit automatically resets to zero
13 ADC_
FULLSCALE		 R/W 1b

ADC input voltage range. When input voltage is below 5V, or battery is 1S, full scale 2.04V is recommended.

0b: 2.04 V

1b: 3.06 V <default at POR>
12-8 Reserved R/W 00000b Reserved

Table 20. ADCOption Register (SMBus address = 35h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
7 EN_ADC_CMPIN R/W 0b

0b: Disable <default at POR>

1b: Enable
6 EN_ADC_VBUS R/W 0b

0b: Disable <default at POR>

1b: Enable

5 EN_ADC_PSYS R/W 0b

0b: Disable <default at POR>

1b: Enable
4 EN_ADC_IIN R/W 0b

0b: Disable <default at POR>

1b: Enable
3 EN_ADC_IDCHG R/W 0b

0b: Disable <default at POR>

1b: Enable
2 EN_ADC_ICHG R/W 0b

0b: Disable <default at POR>

1b: Enable
1 EN_ADC_VSYS R/W 0b

0b: Disable <default at POR>

1b: Enable
0 EN_ADC_VBAT R/W 0b

0b: Disable <default at POR>

1b: Enable

8.6.2 Charge and PROCHOT Status

8.6.2.1 ChargerStatus Register (SMBus address = 20h) [reset = 0000h]

Figure 20. ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
15 14 13 12 11 10 9 8
AC_STAT ICO_DONE Reserved IN_VINDPM IN_IINDPM IN_FCHRG IN_PCHRG Reserved
R R R R R R R R
7 6 5 4 3 2 1 0
Fault ACOV Fault BATOC Fault ACOC SYSOVP_
STAT		 Reserved Fault Latchoff Reserved Reserved
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21. ChargerStatus Register (SMBus address = 20h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
15 AC_STAT R 0b

Input source status, same as CHRG_OK pin

0b: Input not present

1b: Input is present
14 ICO_DONE R 0b

After the ICO routine is successfully executed, the bit goes 1.

0b: ICO is not complete

1b: ICO is complete
13 Reserved R 0b

Reserved
12 IN_VINDPM R 0b

0b: Charger is not in VINDPM during forward mode

1b: Charger is in VINDPM during forward mode
11 IN_IINDPM R 0b

0b: Charger is not in IINDPM

1b: Charger is in IINDPM

10 IN_FCHRG R 0b

0b: Charger is not in fast charge

1b: Charger is in fast charger
9 IN_PCHRG R 0b

0b: Charger is not in pre-charge

1b: Charger is in pre-charge
8 Reserved R Reserved

Table 22. ChargerStatus Register (SMBus address = 20h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
7 Fault ACOV R 0b

The faults are latched until a read from host.

0b: No fault

1b: ACOV
6 Fault BATOC R 0b

The faults are latched until a read from host.

0b: No fault

1b: BATOC
5 Fault ACOC R 0b

The faults are latched until a read from host.

0b: No fault

1b: ACOC
4 SYSOVP_STAT R 0b

SYSOVP Status and Clear

When the SYSOVP occurs, this bit is HIGH. During the SYSOVP, the converter is disabled.

After the SYSOVP is removed, the user must write a 0 to this bit or unplug the adapter to clear the SYSOVP condition to enable the converter again.

0b: Not in SYSOVP <default at POR>

1b: In SYSOVP. When SYSOVP is removed, write 0 to clear the SYSOVP latch.

3 Reserved R 0b Reserved
2 Fault Latchoff R 0b

The faults are latched until a read from host.

0b: No fault

1b: Latch off (REG0x30[3])

1 Reserved R Reserved
0 Reserved R Reserved

8.6.2.2 ProchotStatus Register (SMBus address = 21h) [reset = 0h]

Figure 21. ProchotStatus Register (SMBus address = 21h) [reset = 0h]
15-8
Reserved
R
7 6 5 4 3 2 1 0
Reserved STAT_COMP STAT_ICRIT STAT_INOM STAT_IDCHG STAT_VSYS STAT_Battery_Removal STAT_Adapter_Removal
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23. ProchotStatus Register (SMBus address = 21h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
15-8 Reserved R 00000000b

Reserved

Table 24. ProchotStatus Register (SMBus address = 21h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
7 Reserved R 0b

Reserved
6 STAT_COMP R 0b

0b: Not triggered

1b: Triggered
5 STAT_ICRIT R 0b

0b: Not triggered

1b: Triggered
4 STAT_INOM R 0b

0b: Not triggered

1b: Triggered
3 STAT_IDCHG R 0b

0b: Not triggered

1b: Triggered

2 STAT_VSYS R 0b

0b: Not triggered

1b: Triggered
1 STAT_Battery_Removal R 0b

0b: Not triggered

1b: Triggered
0 STAT_Adapter_Removal R 0b

0b: Not triggered

1b: Triggered

8.6.3 ChargeCurrent Register (SMBus address = 14h) [reset = 0h]

To set the charge current, write a 16-bit ChargeCurrent() command (REG0x14()) using the data format listed in Figure 22

With 10-mΩ sense resistor, the charger provides charge current range of 64 mA to 8.128 A, with a 64-mA step resolution. Upon POR, ChargeCurrent() is 0 A when auto wakeup is not active. Any conditions for CHRG_OK low except ACOV will reset ChargeCurrent() to zero. CELL_BATPRESZ going LOW (battery removal) will reset the ChargeCurrent() register to 0 A.

Charge current is not reset in ACOC, TSHUT, power path latch off (REG0x30[1]), and SYSOVP.

A 0.1-µF capacitor between SRP and SRN for differential mode filtering is recommended; an optional 0.1-µF capacitor between SRN and ground, and an optional 0.1-µF capacitor between SRP and ground for common mode filtering. Meanwhile, the capacitance on SRP should not be higher than 0.1 µF in order to properly sense the voltage across SRP and SRN for cycle-by-cycle current detection.

The SRP and SRN pins are used to sense voltage drop across RSR with default value of 10 mΩ. However, resistors of other values can also be used. For a larger sense resistor, a larger sense voltage is given, and a higher regulation accuracy; but, at the expense of higher conduction loss. A current sensing resistor value no more than 20 mΩ is suggested.

Figure 22. ChargeCurrent Register With 10-mΩ Sense Resistor (SMBus address = 14h) [reset = 0h]
15 14 13 12 11 10 9 8
Reserved Charge Current, bit 6 Charge Current, bit 5 Charge Current, bit 4 Charge Current, bit 3 Charge Current, bit 2
R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
Charge Current, bit 1 Charge Current, bit 0 Reserved Reserved
R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 25. Charge Current Register (14h) With 10-mΩ Sense Resistor (SMBus address = 14h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
15-13 Reserved R/W 000b

Not used. 1 = invalid write.

12 Charge Current, bit 6 R/W 0b

0 = Adds 0 mA of charger current.

1 = Adds 4096 mA of charger current.
11 Charge Current, bit 5 R/W 0b

0 = Adds 0 mA of charger current.

1 = Adds 2048 mA of charger current.
10 Charge Current, bit 4 R/W 0b

0 = Adds 0 mA of charger current.

1 = Adds 1024 mA of charger current.
9 Charge Current, bit 3 R/W 0b

0 = Adds 0 mA of charger current.

1 = Adds 512 mA of charger current.
8 Charge Current, bit 2 R/W 0b

0 = Adds 0 mA of charger current.

1 = Adds 256 mA of charger current.

Table 26. Charge Current Register (14h) With 10-mΩ Sense Resistor (SMBus address = 14h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
7 Charge Current, bit 1 R/W 0b

0 = Adds 0 mA of charger current.

1 = Adds 128 mA of charger current.
6 Charge Current, bit 0 R/W 0b

0 = Adds 0 mA of charger current.

1 = Adds 64 mA of charger current.
5-0 Reserved R/W 000000b

Not used. Value Ignored.

8.6.3.1 Battery Pre-Charge Current Clamp

During pre-charge, BATFET works in linear mode or LDO mode (default REG0x12[2] = 1). For 2-4 cell battery, the system is regulated at minimum system voltage in REG0x3E() and the pre-charge current is clamped at 384 mA. For 1 cell battery, the pre-charge to fast charge threshold is 3V, and the pre-charge current is clamped at 384mA. However, the BATFET stays in LDO mode operation till battery voltage is above minimum system voltage (~3.6V). During battery voltage from 3V to 3.6V, the fast charge current is clamped at 2A.

8.6.4 MaxChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting]

To set the output charge voltage, write a 16-bit ChargeVoltage register command (REG0x15()) using the data format listed in Figure 23. The charger provides charge voltage range from 1.024 V to 19.200 V, with 16-mV step resolution. Any write below 1.024 V or above 19.200 V is ignored.

Upon POR, REG0x15() is by default set as 4192 mV for 1 s, 8400 mV for 2 s, 12592 mV for 3 s or 16800 mV for 4 s. After CHRG_OK, if host writes REG0x14() before REG0x15(), the charge will start after the write to REG0x14().If the battery is different from 4.2 V/cell, the host has to write to REG0x15() before REG0x14() for correct battery voltage setting. Writing REG0x15() to 0 will set REG0x15() to default value on CELL_BATPRESZ pin, and force REG0x14() to zero to disable charge.

The SRN pin is used to sense the battery voltage for voltage regulation and should be connected as close to the battery as possible, and directly place a decoupling capacitor (0.1-µF recommended) as close to the device as possible to decouple high frequency noise.

Figure 23. MaxChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting]
15 14 13 12 11 10 9 8
Reserved Max Charge Voltage, bit 10 Max Charge Voltage, bit 9 Max Charge Voltage, bit 8 Max Charge Voltage, bit 7 Max Charge Voltage, bit 6 Max Charge Voltage, bit 5 Max Charge Voltage, bit 4
R/W R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
Max Charge Voltage, bit 3 Max Charge Voltage, bit 2 Max Charge Voltage, bit 1 Max Charge Voltage, bit 0 Reserved
R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27. MaxChargeVoltage Register (SMBus address = 15h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
15 Reserved R/W 0b

Not used. 1 = invalid write.

14 Max Charge Voltage, bit 10 R/W 0b

0 = Adds 0 mV of charger voltage.

1 = Adds 16384 mV of charger voltage.
13 Max Charge Voltage, bit 9 R/W 0b

0 = Adds 0 mV of charger voltage.

1 = Adds 8192 mV of charger voltage
12 Max Charge Voltage, bit 8 R/W 0b

0 = Adds 0 mV of charger voltage.

1 = Adds 4096 mV of charger voltage.
11 Max Charge Voltage, bit 7 R/W 0b

0 = Adds 0 mV of charger voltage.

1 = Adds 2048 mV of charger voltage.
10 Max Charge Voltage, bit 6 R/W 0b

0 = Adds 0 mV of charger voltage.

1 = Adds 1024 mV of charger voltage.
9 Max Charge Voltage, bit 5 R/W 0b

0 = Adds 0 mV of charger voltage.

1 = Adds 512 mV of charger voltage.
8 Max Charge Voltage, bit 4 R/W 0b

0 = Adds 0 mV of charger voltage.

1 = Adds 256 mV of charger voltage.

Table 28. MaxChargeVoltage Register (SMBus address = 15h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
7 Max Charge Voltage, bit 3 R/W 0b

0 = Adds 0 mV of charger voltage.

1 = Adds 128 mV of charger voltage.
6 Max Charge Voltage, bit 2 R/W 0b

0 = Adds 0 mV of charger voltage.

1 = Adds 64 mV of charger voltage.
5 Max Charge Voltage, bit 1 R/W 0b

0 = Adds 0 mV of charger voltage.

1 = Adds 32 mV of charger voltage.

4 Max Charge Voltage, bit 0 R/W 0b

0 = Adds 0 mV of charger voltage.

1 = Adds 16 mV of charger voltage.
3-0 Reserved R/W 0000b

Not used. Value Ignored.

8.6.5 MinSystemVoltage Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]

To set the minimum system voltage, write a 16-bit MinSystemVoltage register command (REG0x3E()) using the data format listed in Figure 25. The charger provides minimum system voltage range from 1.024 V to 16.128 V, with 256-mV step resolution. Any write below 1.024 V or above 16.128 V is ignored. Upon POR, the MinSystemVoltage register is 3.584 V for 1 S, 6.144 V for 2 S and 9.216 V for 3 S, and 12.288 V for 4 S.

Figure 24. MinSystemVoltage Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
15 14 13 12 11 10 9 8
Reserved Min System Voltage, bit 5 Min System Voltage, bit 4 Min System Voltage, bit 3 Min System Voltage, bit 2 Min System Voltage, bit 1 Min System Voltage, bit 0
R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
Reserved
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 29. MinSystemVoltage Register (SMBus address = 3Eh) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
15-14 Reserved R/W 00b

Not used. 1 = invalid write.
13 Min System Voltage, bit 5 R/W 0b

0 = Adds 0 mV of system voltage.

1 = Adds 8192 mV of system voltage.
12 Min System Voltage, bit 4 R/W 0b

0 = Adds 0 mV of system voltage.

1 = Adds 4096mV of system voltage.
11 Min System Voltage, bit 3 R/W 0b

0 = Adds 0 mV of system voltage.

1 = Adds 2048 mV of system voltage.
10 Min System Voltage, bit 2 R/W 0b

0 = Adds 0 mV of system voltage.

1 = Adds 1024 mV of system voltage.
9 Min System Voltage, bit 1 R/W 0b

0 = Adds 0 mV of system voltage.

1 = Adds 512 mV of system voltage.
8 Min System Voltage, bit 0 R/W 0b

0 = Adds 0 mV of system voltage.

1 = Adds 256 mV of system voltage.

Table 30. MinSystemVoltage Register (SMBus address = 3Eh) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
7-0 Reserved R/W 00000000b

Not used. Value Ignored.

8.6.5.1 System Voltage Regulation

The device employs Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by REG0x3E(). Even with a deeply depleted battery, the system is regulated above the minimum system voltage with BATFET.

When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode), and the system is regulated above the minimum system voltage setting. As the battery voltage rises above the minimum system voltage, BATFET is fully on when charging or in supplement mode and the voltage difference between the system and battery is the VDS of BATFET. System voltage is regulated 160mV above battery voltage when BATFET is off (no charging or no supplement current).

When BATFET is removed, the system node VSYS is shorted to SRP. Before the converter starts operation, LDO mode needs to be disabled. The following sequence is required to configure charger without BATFET.

  1. Before adapter plugs in, put the charger into HIZ mode. (either pull pin 6 ILIM_HIZ to ground, or set REG0x32[15] to 1)
  2. Set 0x12[2] to 0 to disable LDO mode.
  3. Set 0x30[0] to 0 to disable auto-wakeup mode.
  4. Check if battery voltage is properly programmed (REG0x15)
  5. Set pre-charge/charge current (REG0x14)
  6. Put the device out of HIZ mode. (Release ILIM_HIZ from ground and set REG0x32[15]=0).

In order to prevent any accidental SW mistakes, the host sets low input current limit (a few hundred milliamps) when device is out of HIZ.

8.6.6 Input Current and Input Voltage Registers for Dynamic Power Management

The charger supports Dynamic Power Management (DPM). Normally, the input power source provides power for the system load or to charge the battery. When the input current exceeds the input current setting, or the input voltage falls below the input voltage setting, the charger decreases the charge current to provide priority to the system load. As the system current rises, the available charge current drops accordingly towards zero. If the system load keeps increasing after the charge current drops down to zero, the system voltage starts to drop. As the system voltage drops below the battery voltage, the battery will discharge to supply the heavy system load.

8.6.6.1 Input Current Registers

To set the maximum input current limit, write a 16-bit IIN_HOST register command (REG0x3F()) using the data format listed in Figure 25. When using a 10-mΩ sense resistor, the charger provides an input-current limit range of 50 mA to 6400 mA, with 50-mA resolution. The default current limit is 3.3 A. Due to the USB current setting requirement, the register setting specifies the maximum current instead of the typical current. Upon adapter removal, the input current limit is reset to the default value of 3.3 A. The register setting is clamped at 50mA. With code 00h and 01h, the input current limit settings are both 50mA.

The ACP and ACN pins are used to sense RAC with the default value of 10 mΩ. For a 20 mΩ sense resistor, a larger sense voltage is given and a higher regulation accuracy, but at the expense of higher conduction loss.

Instead of using the internal DPM loop, the user can build up an external input current regulation loop and have the feedback signal on the ILIM_HIZ pin.

Equation 2. bq25708 equation_SLUSCK9.gif

In order to disable ILIM_HIZ pin, the host can write to 0x31[7] to disable ILIM_HIZ pin, or pull ILIM_HIZ pin above 4 V.

8.6.6.1.1 IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4000h]

Figure 25. IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4100h]
15 14 13 12 11 10 9 8
Reserved Input Current set by host, bit 6 Input Current set by host, bit 5 Input Current set by host, bit 4 Input Current set by host, bit 3 Input Current set by host, bit 2 Input Current set by host, bit 1 Input Current set by host, bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 31. IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
15 Reserved R 0b

Not used. 1 = invalid write.
14 Input Current set by host, bit 6 R 1b

0 = Adds 0 mA of input current.

1 = Adds 3200 mA of input current.
13 Input Current set by host, bit 5 R 0b

0 = Adds 0 mA of input current.

1 = Adds 1600 mA of input current.
12 Input Current set by host, bit 4 R 0b

0 = Adds 0 mA of input current.

1 = Adds 800 mA of input current.
11 Input Current set by host, bit 3 R 0b

0 = Adds 0 mA of input current.

1 = Adds 400 mA of input current.
10 Input Current set by host, bit 2 R 0b

0 = Adds 0 mA of input current.

1 = Adds 200 mA of input current.
9 Input Current set by host, bit 1 R 0b

0 = Adds 0 mA of input current.

1 = Adds 100 mA of input current.
8 Input Current set by host, bit 0 R 0b

0 = Adds 0 mA of input current.

1 = Adds 50 mA of input current.

Table 32. IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
7-0 Reserved R 00000000b

Not used. Value Ignored.

8.6.6.1.2 IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) [reset = 0h]

IIN_DPM register reflects the actual input current limit programmed in the register, either from host or from ICO.

After ICO, the current limit used by DPM regulation may differ from the IIN_HOST register settings. The actual DPM limit is reported in REG0x22().

Figure 26. IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) [reset = 0h]
15 14 13 12 11 10 9 8
Reserved Input Current in DPM, bit 6 Input Current in DPM, bit 5 Input Current in DPM, bit 4 Input Current in DPM, bit 3 Input Current in DPM, bit 2 Input Current in DPM, bit 1 Input Current in DPM, bit 0
R R R R R R R R
7 6 5 4 3 2 1 0
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 33. IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
15 Reserved R 0b

Not used. 1 = invalid write.
14 Input Current in DPM, bit 6 R 0b

0 = Adds 0 mA of input current.

1 = Adds 3200 mA of input current.
13 Input Current in DPM, bit 5 R 0b

0 = Adds 0 mA of input current.

1 = Adds 1600 mA of input current.
12 Input Current in DPM, bit 4 R 0b

0 = Adds 0 mA of input current.

1 = Adds 800mA of input current
11 Input Current in DPM, bit 3 R 0b

0 = Adds 0 mA of input current.

1 = Adds 400 mA of input current.
10 Input Current in DPM, bit 2 R 0b

0 = Adds 0 mA of input current.

1 = Adds 200 mA of input current.
9 Input Current in DPM, bit 1 R 0b

0 = Adds 0 mA of input current.

1 = Adds 100 mA of input current.
8 Input Current in DPM, bit 0 R 0b

0 = Adds 0 mA of input current.

1 = Adds 50 mA of input current.

Table 34. IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
7-0 Reserved R 00000000b

Not used. Value Ignored.

8.6.6.1.3 InputVoltage Register (SMBus address = 3Dh) [reset = VBUS-1.28V]

To set the input voltage limit, write a 16-bit InputVoltage register command (REG0x3D()) using the data format listed in Figure 27.

If the input voltage drops more than the InputVoltage register allows, the device enters DPM and reduces the charge current. The default offset voltage is 1.28 V below the no-load VBUS voltage. The DC offset is 3.2 V (0000000).

Figure 27. InputVoltage Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
15 14 13 12 11 10 9 8
Reserved Input Voltage, bit 7 Input Voltage, bit 6 Input Voltage, bit 5 Input Voltage, bit 4 Input Voltage, bit 3 Input Voltage, bit 2
R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
Input Voltage, bit 1 Input Voltage, bit 0 Reserved
R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 35. InputVoltage Register (SMBus address = 3Dh) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
15-14 Reserved R/W 00b

Not used. 1 = invalid write.
13 Input Voltage, bit 7 R/W 0b

0 = Adds 0 mV of input voltage.

1 = Adds 8192 mV of input voltage.
12 Input Voltage, bit 6 R/W 0b

0 = Adds 0 mV of input voltage.

1 = Adds 4096mV of input voltage.
11 Input Voltage, bit 5 R/W 0b

0 = Adds 0 mV of input voltage.

1 = Adds 2048 mV of input voltage.
10 Input Voltage, bit 4 R/W 0b

0 = Adds 0 mV of input voltage.

1 = Adds 1024 mV of input voltage.
9 Input Voltage, bit 3 R/W 0b

0 = Adds 0 mV of input voltage.

1 = Adds 512 mV of input voltage.
8 Input Voltage, bit 2 R/W 0b

0 = Adds 0 mV of input voltage.

1 = Adds 256 mV of input voltage.

Table 36. InputVoltage Register (SMBus address = 3Dh) Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
7 Input Voltage, bit 1 R/W 0b

0 = Adds 0 mV of input voltage.

1 = Adds 128 mV of input voltage.
6 Input Voltage, bit 0 R/W 0b

0 = Adds 0 mV of input voltage.

1 = Adds 64 mV of input voltage
5-0 Reserved R/W 000000b

Not used. Value Ignored.

8.6.7 ADCVBUS/PSYS Register (SMBus address = 23h)

  • PSYS: Full range: 3.06 V, LSB: 12 mV
  • VBUS: Full range: 3200 mV to 19520 mV, LSB: 64 mV
Figure 28. ADCVBUS/PSYS Register (SMBus address = 23h)
15 14 13 12 11 10 9 8
R R R R R R R R
7 6 5 4 3 2 1 0
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 37. ADCVBUS/PSYS Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
15-8 R 8-bit Digital Output of Input Voltage
7-0 R 8-bit Digital Output of System Power

8.6.8 ADCIBAT Register (SMBus address = 24h)

  • ICHG: Full range: 8.128 A, LSB 64: mA
  • IDCHG: Full range: 32.512 A, LSB: 256 mA
Figure 29. ADCIBAT Register (SMBus address = 24h)
15 14 13 12 11 10 9 8
Reserved R R R R R R R
7 6 5 4 3 2 1 0
Reserved R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 38. ADCIBAT Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
15 Reserved R Not used. Value ignored.
14-8 R 7-bit Digital Output of Battery Charge Current
7 Reserved R Not used. Value ignored.
6-0 R 7-bit Digital Output of Battery Discharge Current

8.6.9 ADCIINCMPIN Register (SMBus address = 25h)

  • IIN: Full range: 12.75 A, LSB: 50 mA
  • CMPIN: Full range: 3.06 V, LSB: 12 mV
Figure 30. ADCIINCMPIN Register (SMBus address = 25h)
15 14 13 12 11 10 9 8
R R R R R R R R
7 6 5 4 3 2 1 0
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 39. ADCIINCMPIN Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
15-8 R 8-bit Digital Output of Input Current
7-0 R 8-bit Digital Output of CMPIN voltage

8.6.10 ADCVSYSVBAT Register (SMBus address = 26h) (reset = )

  • VSYS: Full range: 2.88 V to 19.2 V, LSB: 64 mV
  • VBAT: Full range: 2.88 V to 19.2 V, LSB: 64 mV
Figure 31. ADCVSYSVBAT Register (SMBus address = 26h) (reset = )
15 14 13 12 11 10 9 8
R R R R R R R R
7 6 5 4 3 2 1 0
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 40. ADCVSYSVBAT Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
15-8 R 8-bit Digital Output of System Voltage
7-0 R 8-bit Digital Output of Battery Voltage

8.6.11 ID Registers

8.6.11.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h]

Figure 32. ManufactureID Register (SMBus address = FEh) [reset = 0040h]
15-0
MANUFACTURE_ID
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 41. ManufactureID Register Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION (READ ONLY)
15-0 MANUFACTURE_ID R

40h

8.6.11.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 0h]

Figure 33. Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 0h]
15-8
Reserved
R
7-0
DEVICE_ID
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 42. Device ID (DeviceAddress) Register Field Descriptions

SMBus
BIT		 FIELD TYPE RESET DESCRIPTION (READ ONLY)
15-8 Reserved R 0b

Reserved
7-0 DEVICE_ID R 0b

SMBus: 7Ch