SLUSCU2 November   2017

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-Up from Battery Without DC Source
      2. 8.3.2 Power-Up From DC Source
        1. 8.3.2.1 CHRG_OK Indicator
        2. 8.3.2.2 Input Voltage and Current Limit Setup
        3. 8.3.2.3 Battery Cell Configuration
        4. 8.3.2.4 Device Hi-Z State
      3. 8.3.3 Converter Operation
        1. 8.3.3.1 Inductor Setting through IADPT Pin
        2. 8.3.3.2 Continuous Conduction Mode (CCM)
        3. 8.3.3.3 Pulse Frequency Modulation (PFM)
      4. 8.3.4 Current and Power Monitor
        1. 8.3.4.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 8.3.4.2 High-Accuracy Power Sense Amplifier (PSYS)
      5. 8.3.5 Input Source Dynamic Power Manage
      6. 8.3.6 Two-Level Adapter Current Limit (Peak Power Mode)
      7. 8.3.7 Processor Hot Indication
        1. 8.3.7.1 PROCHOT During Low Power Mode
        2. 8.3.7.2 PROCHOT Status
      8. 8.3.8 Device Protection
        1. 8.3.8.1 Watchdog Timer
        2. 8.3.8.2 Input Overvoltage Protection (ACOV)
        3. 8.3.8.3 Input Overcurrent Protection (ACOC)
        4. 8.3.8.4 System Overvoltage Protection (SYSOVP)
        5. 8.3.8.5 Battery Overvoltage Protection (BATOVP)
        6. 8.3.8.6 Battery Short
        7. 8.3.8.7 Thermal Shutdown (TSHUT)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forward Mode
        1. 8.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 8.4.1.2 Battery Charging
    5. 8.5 Programming
      1. 8.5.1 SMBus Interface
        1. 8.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 8.5.1.2 Timing Diagrams
    6. 8.6 Register Map
      1. 8.6.1  Setting Charge and PROCHOT Options
        1. 8.6.1.1 ChargeOption0 Register (SMBus address = 12h) [reset = E20Eh]
        2. 8.6.1.2 ChargeOption1 Register (SMBus address = 30h) [reset = 211h]
        3. 8.6.1.3 ChargeOption2 Register (SMBus address = 31h) [reset = 2B7]
        4. 8.6.1.4 ChargeOption3 Register (SMBus address = 32h) [reset = 0h]
        5. 8.6.1.5 ProchotOption0 Register (SMBus address = 33h) [reset = 04A54h]
        6. 8.6.1.6 ProchotOption1 Register (SMBus address = 34h) [reset = 8120h]
        7. 8.6.1.7 ADCOption Register (SMBus address = 35h) [reset = 2000h]
      2. 8.6.2  Charge and PROCHOT Status
        1. 8.6.2.1 ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
        2. 8.6.2.2 ProchotStatus Register (SMBus address = 21h) [reset = 0h]
      3. 8.6.3  ChargeCurrent Register (SMBus address = 14h) [reset = 0h]
        1. 8.6.3.1 Battery Pre-Charge Current Clamp
      4. 8.6.4  MaxChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting]
      5. 8.6.5  MinSystemVoltage Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
        1. 8.6.5.1 System Voltage Regulation
      6. 8.6.6  Input Current and Input Voltage Registers for Dynamic Power Management
        1. 8.6.6.1 Input Current Registers
          1. 8.6.6.1.1 IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4000h]
          2. 8.6.6.1.2 IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) [reset = 0h]
          3. 8.6.6.1.3 InputVoltage Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
      7. 8.6.7  ADCVBUS/PSYS Register (SMBus address = 23h)
      8. 8.6.8  ADCIBAT Register (SMBus address = 24h)
      9. 8.6.9  ADCIINCMPIN Register (SMBus address = 25h)
      10. 8.6.10 ADCVSYSVBAT Register (SMBus address = 26h) (reset = )
      11. 8.6.11 ID Registers
        1. 8.6.11.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h]
        2. 8.6.11.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 0h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 ACP-ACN Input Filter
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Input Capacitor
        4. 9.2.2.4 Output Capacitor
        5. 9.2.2.5 Power MOSFETs Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Layout Consideration of Current Path
      2. 11.2.2 Layout Consideration of Short Circuit Protection
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.