SLUSD20B july   2018  – april 2023 BQ25710

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power-Up from Battery Without DC Source
      2. 9.3.2  Vmin Active Protection (VAP) when Battery only Mode
      3. 9.3.3  Power-Up From DC Source
        1. 9.3.3.1 CHRG_OK Indicator
        2. 9.3.3.2 Input Voltage and Current Limit Setup
        3. 9.3.3.3 Battery Cell Configuration
        4. 9.3.3.4 Device Hi-Z State
      4. 9.3.4  USB On-The-Go (OTG)
      5. 9.3.5  Converter Operation
        1. 9.3.5.1 Inductance Detection Through IADPT Pin
        2. 9.3.5.2 Continuous Conduction Mode (CCM)
        3. 9.3.5.3 Pulse Frequency Modulation (PFM)
      6. 9.3.6  Current and Power Monitor
        1. 9.3.6.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 9.3.6.2 High-Accuracy Power Sense Amplifier (PSYS)
      7. 9.3.7  Input Source Dynamic Power Manage
      8. 9.3.8  Two-Level Adapter Current Limit (Peak Power Mode)
      9. 9.3.9  Processor Hot Indication
        1. 9.3.9.1 PROCHOT During Low Power Mode
        2. 9.3.9.2 PROCHOT Status
      10. 9.3.10 Device Protection
        1. 9.3.10.1 Watchdog Timer
        2. 9.3.10.2 Input Overvoltage Protection (ACOV)
        3. 9.3.10.3 Input Overcurrent Protection (ACOC)
        4. 9.3.10.4 System Overvoltage Protection (SYSOVP)
        5. 9.3.10.5 Battery Overvoltage Protection (BATOVP)
        6. 9.3.10.6 Battery Short
        7. 9.3.10.7 System Short Hiccup Mode
        8. 9.3.10.8 Thermal Shutdown (TSHUT)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Forward Mode
        1. 9.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 9.4.1.2 Battery Charging
      2. 9.4.2 USB On-The-Go
      3. 9.4.3 Pass Through Mode (PTM)
    5. 9.5 Programming
      1. 9.5.1 SMBus Interface
        1. 9.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 9.5.1.2 Timing Diagrams
    6. 9.6 Register Map
      1. 9.6.1  Setting Charge and PROCHOT Options
        1. 9.6.1.1 ChargeOption0 Register (SMBus address = 12h) [reset = E70Eh]
        2. 9.6.1.2 ChargeOption1 Register (SMBus address = 30h) [reset = 0211h]
        3. 9.6.1.3 ChargeOption2 Register (SMBus address = 31h) [reset = 02B7h]
        4. 9.6.1.4 ChargeOption3 Register (SMBus address = 32h) [reset = 0030h]
        5. 9.6.1.5 ProchotOption0 Register (SMBus address = 33h) [reset = 4A65h]
        6. 9.6.1.6 ProchotOption1 Register (SMBus address = 34h) [reset = 81A0h]
        7. 9.6.1.7 ADCOption Register (SMBus address = 35h) [reset = 2000h]
      2. 9.6.2  Charge and PROCHOT Status
        1. 9.6.2.1 ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
        2. 9.6.2.2 ProchotStatus Register (SMBus address = 21h) [reset = A800h]
      3. 9.6.3  ChargeCurrent Register (SMBus address = 14h) [reset = 0000h]
        1. 9.6.3.1 Battery Precharge Current Clamp
      4. 9.6.4  MaxChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting]
      5. 9.6.5  MinSystemVoltage Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
        1. 9.6.5.1 System Voltage Regulation
      6. 9.6.6  Input Current and Input Voltage Registers for Dynamic Power Management
        1. 9.6.6.1 Input Current Registers
          1. 9.6.6.1.1 IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4100h]
          2. 9.6.6.1.2 IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) [reset = 4100h]
          3. 9.6.6.1.3 InputVoltage Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
      7. 9.6.7  OTGVoltage Register (SMBus address = 3Bh) [reset = 0000h]
      8. 9.6.8  OTGCurrent Register (SMBus address = 3Ch) [reset = 0000h]
      9. 9.6.9  ADCVBUS/PSYS Register (SMBus address = 23h)
      10. 9.6.10 ADCIBAT Register (SMBus address = 24h)
      11. 9.6.11 ADCIINCMPIN Register (SMBus address = 25h)
      12. 9.6.12 ADCVSYSVBAT Register (SMBus address = 26h)
      13. 9.6.13 ID Registers
        1. 9.6.13.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h]
        2. 9.6.13.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 0h]
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 ACP-ACN Input Filter
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Input Capacitor
        4. 10.2.2.4 Output Capacitor
        5. 10.2.2.5 Power MOSFETs Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
      1. 12.2.1 Layout Example Reference Top View
      2. 12.2.2 Inner Layer Layout and Routing Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12.1 Layout Guidelines

Proper layout of the components to minimize high frequency current path loop (see Section 12.2) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout.

Table 12-1 PCB Layout Guidelines
RULES COMPONENTS FUNCTION IMPACT GUIDELINES
1 PCB layer stack up Thermal, efficiency, signal integrity Multi- layer PCB is suggested. Allocate at least one ground layer. The BQ257XXEVM uses a 4-layer PCB (top layer, ground layer, signal layer and bottom layer).
2 CBUS, RAC, Q1, Q2 Input loop High frequency noise, ripple VBUS capacitors, RAC, Q1 and Q2 form a small loop 1. It is best to put them on the same side. Connect them with large copper to reduce the parasitic resistance. Move part of CBUS to the other side of PCB for high density design. After RAC before Q1 and Q2 power stage recommend to put 10 nF + 1 nF (0402 package) decoupling capacitors as close as possible to IC to decoupling switching loop high frequency noise.
3 RAC, Q1, L1, Q4 Current path Efficiency The current path from VBUS to VSYS, through RAC, Q1, L1, Q4, has low impedance. Pay attention to via resistance if they are not on the same side. The number of vias can be estimated as 1 to 2A/via for a 10-mil via with 1 oz. copper thickness.
4 CSYS, Q3, Q4 Output loop High frequency noise, ripple VSYS capacitors, Q3 and Q4 form a small loop 2. It is best to put them on the same side. Connect them with large copper to reduce the parasitic resistance. Move part of CSYS to the other side of PCB for high density design.
5 QBAT, RSR Current path Efficiency, battery voltage detection Place QBAT and RSR near the battery terminal. The current path from VBAT to VSYS, through RSRand QBAT, has low impedance. Pay attention to via resistance if they are not on the same side. The device detects the battery voltage through SRN near battery terminal.
6 Q1, Q2, L1, Q3, Q4 Power stage Thermal, efficiency Place Q1, Q2, L1, Q3 and Q4 next to each other. Allow enough copper area for thermal dissipation. The copper area is suggested to be 2x to 4x of the pad size. Multiple thermal vias can be used to connect more copper layers together and dissipate more heat.
7 RAC, RSR Current sense Regulation accuracy Use Kelvin-sensing technique for RAC and RSR current sense resistors. Connect the current sense traces to the center of the pads, and run current sense traces as differential pairs.
8 Small capacitors IC bypass caps Noise, jittering, ripple Place VBUS cap, VCC cap, REGN caps near IC.
9 BST capacitors HS gate drive High frequency noise, ripple Place HS MOSFET boost strap circuit capacitor close to IC and on the same side of PCB board. Capacitors SW1/2 nodes are recommended to use wide copper polygon to connect to power stage and capacitors BST1/2 node are recommended to use at least 8mil trace to connected to IC BST1/2 pins.
10 Ground partition Measurement accuracy, regulation accuracy, jitters, ripple Separate analog ground(AGND) and power grounds(PGND) is preferred. PGND should be used for all power stage related ground net. AGND should be used for all sensing, compensation and control network ground for example ACP/ACN/COMP1/COMP2/CMPIN/CMPOUT/IADPT/IBAT/PSYS. Connect all analog grounds to a dedicated low-impedance copper plane, which is tied to the power ground underneath the IC exposed pad. If possible, use dedicated COMP1, COMP2 AGND traces. Connect analog ground and power ground together using power pad as the single ground connection point.