SLUSD20B july   2018  – april 2023 BQ25710

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power-Up from Battery Without DC Source
      2. 9.3.2  Vmin Active Protection (VAP) when Battery only Mode
      3. 9.3.3  Power-Up From DC Source
        1. 9.3.3.1 CHRG_OK Indicator
        2. 9.3.3.2 Input Voltage and Current Limit Setup
        3. 9.3.3.3 Battery Cell Configuration
        4. 9.3.3.4 Device Hi-Z State
      4. 9.3.4  USB On-The-Go (OTG)
      5. 9.3.5  Converter Operation
        1. 9.3.5.1 Inductance Detection Through IADPT Pin
        2. 9.3.5.2 Continuous Conduction Mode (CCM)
        3. 9.3.5.3 Pulse Frequency Modulation (PFM)
      6. 9.3.6  Current and Power Monitor
        1. 9.3.6.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 9.3.6.2 High-Accuracy Power Sense Amplifier (PSYS)
      7. 9.3.7  Input Source Dynamic Power Manage
      8. 9.3.8  Two-Level Adapter Current Limit (Peak Power Mode)
      9. 9.3.9  Processor Hot Indication
        1. 9.3.9.1 PROCHOT During Low Power Mode
        2. 9.3.9.2 PROCHOT Status
      10. 9.3.10 Device Protection
        1. 9.3.10.1 Watchdog Timer
        2. 9.3.10.2 Input Overvoltage Protection (ACOV)
        3. 9.3.10.3 Input Overcurrent Protection (ACOC)
        4. 9.3.10.4 System Overvoltage Protection (SYSOVP)
        5. 9.3.10.5 Battery Overvoltage Protection (BATOVP)
        6. 9.3.10.6 Battery Short
        7. 9.3.10.7 System Short Hiccup Mode
        8. 9.3.10.8 Thermal Shutdown (TSHUT)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Forward Mode
        1. 9.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 9.4.1.2 Battery Charging
      2. 9.4.2 USB On-The-Go
      3. 9.4.3 Pass Through Mode (PTM)
    5. 9.5 Programming
      1. 9.5.1 SMBus Interface
        1. 9.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 9.5.1.2 Timing Diagrams
    6. 9.6 Register Map
      1. 9.6.1  Setting Charge and PROCHOT Options
        1. 9.6.1.1 ChargeOption0 Register (SMBus address = 12h) [reset = E70Eh]
        2. 9.6.1.2 ChargeOption1 Register (SMBus address = 30h) [reset = 0211h]
        3. 9.6.1.3 ChargeOption2 Register (SMBus address = 31h) [reset = 02B7h]
        4. 9.6.1.4 ChargeOption3 Register (SMBus address = 32h) [reset = 0030h]
        5. 9.6.1.5 ProchotOption0 Register (SMBus address = 33h) [reset = 4A65h]
        6. 9.6.1.6 ProchotOption1 Register (SMBus address = 34h) [reset = 81A0h]
        7. 9.6.1.7 ADCOption Register (SMBus address = 35h) [reset = 2000h]
      2. 9.6.2  Charge and PROCHOT Status
        1. 9.6.2.1 ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
        2. 9.6.2.2 ProchotStatus Register (SMBus address = 21h) [reset = A800h]
      3. 9.6.3  ChargeCurrent Register (SMBus address = 14h) [reset = 0000h]
        1. 9.6.3.1 Battery Precharge Current Clamp
      4. 9.6.4  MaxChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting]
      5. 9.6.5  MinSystemVoltage Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
        1. 9.6.5.1 System Voltage Regulation
      6. 9.6.6  Input Current and Input Voltage Registers for Dynamic Power Management
        1. 9.6.6.1 Input Current Registers
          1. 9.6.6.1.1 IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4100h]
          2. 9.6.6.1.2 IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) [reset = 4100h]
          3. 9.6.6.1.3 InputVoltage Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
      7. 9.6.7  OTGVoltage Register (SMBus address = 3Bh) [reset = 0000h]
      8. 9.6.8  OTGCurrent Register (SMBus address = 3Ch) [reset = 0000h]
      9. 9.6.9  ADCVBUS/PSYS Register (SMBus address = 23h)
      10. 9.6.10 ADCIBAT Register (SMBus address = 24h)
      11. 9.6.11 ADCIINCMPIN Register (SMBus address = 25h)
      12. 9.6.12 ADCVSYSVBAT Register (SMBus address = 26h)
      13. 9.6.13 ID Registers
        1. 9.6.13.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h]
        2. 9.6.13.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 0h]
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 ACP-ACN Input Filter
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Input Capacitor
        4. 10.2.2.4 Output Capacitor
        5. 10.2.2.5 Power MOSFETs Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
      1. 12.2.1 Layout Example Reference Top View
      2. 12.2.2 Inner Layer Layout and Routing Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.6.1.3 ChargeOption2 Register (SMBus address = 31h) [reset = 02B7h]

Figure 9-8 ChargeOption2 Register (SMBus address = 31h) [reset = 02B7h]
1514131.2111098
PKPWR_TOVLD_DEGEN_PKPWR_
IDPM		EN_PKPWR_
VSYS		PKPWR_
OVLD_STAT		PKPWR_
RELAX_STAT		PKPWR_TMAX[1:0]
R/WR/WR/WR/WR/WR/W
76543210
EN_EXTILIMEN_ICHG
_IDCHG		Q2_OCPACX_OCPEN_ACOCACOC_VTHEN__VTH
R/WR/WR/WR/WR/WR/WR/WR/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-11 ChargeOption2 Register (SMBus address = 31h) Field Descriptions
SMBus
BIT		FIELDTYPERESETDESCRIPTION
15-14PKPWR_
TOVLD_DEG		R/W00b

Input Overload time in Peak Power Mode

00b: 1 ms <default at POR>

01b: 2 ms

10b: 10 ms

11b: 20 ms

13EN_PKPWR_IDPMR/W0b

Enable Peak Power Mode triggered by input current overshoot

If REG0x31[13:12] are 00b, peak power mode is disabled. Upon adapter removal, the bits are reset to 00b.

0b: Disable peak power mode triggered by input current overshoot <default at POR>

1b: Enable peak power mode triggered by input current overshoot.

12EN_PKPWR_VSYSR/W0b

Enable Peak Power Mode triggered by system voltage under-shoot

If REG0x31[13:12] are 00b, peak power mode is disabled. Upon adapter removal, the bits are reset to 00b.

0b: Disable peak power mode triggered by system voltage under-shoot <default at POR>

1b: Enable peak power mode triggered by system voltage under-shoot.

11PKPWR_
OVLD_STAT		R/W0b

Indicator that the device is in overloading cycle. Write 0 to get out of overloading cycle.

0b: Not in peak power mode. <default at POR>

1b: In peak power mode.

10PKPWR_
RELAX_STAT		R/W0b

Indicator that the device is in relaxation cycle. Write 0 to get out of relaxation cycle.

0b: Not in relaxation cycle. <default at POR>

1b: In relaxation mode.

9-8PKPWR_
TMAX[1:0]		R/W10b

Peak power mode overload and relax cycle time.

When REG0x31[15:14] is programmed longer than REG0x31[9:8], there is no relax time.

00b: 5 ms

01b: 10 ms

10b: 20 ms <default at POR>

11b: 40 ms

Table 9-12 ChargeOption2 Register (SMBus address = 31h) Field Descriptions
SMBus
BIT		FIELDTYPERESETDESCRIPTION
7EN_EXTILIMR/W1b

Enable ILIM_HIZ pin to set input current limit

0b: Input current limit is set by REG0x3F.

1b: Input current limit is set by the lower value of ILIM_HIZ pin and REG0x3F. <default at POR>

6EN_ICHG
_IDCHG		R/W0b

0b: IBAT pin as discharge current. <default at POR>

1b: IBAT pin as charge current.

5Q2_OCPR/W1b

Q2 OCP threshold by sensing Q2 VDS

0b: 210 mV

1b: 150 mV <default at POR>

4ACX_OCPR/W1b

Input current OCP threshold by sensing ACP-ACN.

0b: 280 mV

1b: 150 mV <default at POR>

3EN_ACOCR/W0b

ACOC Enable

Input overcurrent (ACOC) protection by sensing the voltage across ACP and ACN. Upon ACOC (after 100-µs blank-out time), converter is disabled.

0b: Disable ACOC <default at POR>

1b: ACOC threshold 133% or 200% ILIM2

2ACOC_VTHR/W1b

ACOC Limit

Set MOSFET OCP threshold as percentage of IDPM with current sensed from RAC.

0b: 133% of ILIM2

1b: 200% of ILIM2 <default at POR>

1EN_BATOCR/W1b

BATOC Enable

Battery discharge overcurrent (BATOC) protection by sensing the voltage across SRN and SRP. Upon BATOC, converter is disabled.

0b: Disable BATOC

1b: BATOC threshold 133% or 200% PROCHOT IDCHG <default at POR>

0BATOC_VTHR/W1b

Set battery discharge overcurrent threshold as percentage of PROCHOT battery discharge current limit.

0b: 133% of PROCHOT IDCHG

1b: 200% of PROCHOT IDCHG <default at POR>