SLUSD20B july   2018  – april 2023 BQ25710

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power-Up from Battery Without DC Source
      2. 9.3.2  Vmin Active Protection (VAP) when Battery only Mode
      3. 9.3.3  Power-Up From DC Source
        1. 9.3.3.1 CHRG_OK Indicator
        2. 9.3.3.2 Input Voltage and Current Limit Setup
        3. 9.3.3.3 Battery Cell Configuration
        4. 9.3.3.4 Device Hi-Z State
      4. 9.3.4  USB On-The-Go (OTG)
      5. 9.3.5  Converter Operation
        1. 9.3.5.1 Inductance Detection Through IADPT Pin
        2. 9.3.5.2 Continuous Conduction Mode (CCM)
        3. 9.3.5.3 Pulse Frequency Modulation (PFM)
      6. 9.3.6  Current and Power Monitor
        1. 9.3.6.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 9.3.6.2 High-Accuracy Power Sense Amplifier (PSYS)
      7. 9.3.7  Input Source Dynamic Power Manage
      8. 9.3.8  Two-Level Adapter Current Limit (Peak Power Mode)
      9. 9.3.9  Processor Hot Indication
        1. 9.3.9.1 PROCHOT During Low Power Mode
        2. 9.3.9.2 PROCHOT Status
      10. 9.3.10 Device Protection
        1. 9.3.10.1 Watchdog Timer
        2. 9.3.10.2 Input Overvoltage Protection (ACOV)
        3. 9.3.10.3 Input Overcurrent Protection (ACOC)
        4. 9.3.10.4 System Overvoltage Protection (SYSOVP)
        5. 9.3.10.5 Battery Overvoltage Protection (BATOVP)
        6. 9.3.10.6 Battery Short
        7. 9.3.10.7 System Short Hiccup Mode
        8. 9.3.10.8 Thermal Shutdown (TSHUT)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Forward Mode
        1. 9.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 9.4.1.2 Battery Charging
      2. 9.4.2 USB On-The-Go
      3. 9.4.3 Pass Through Mode (PTM)
    5. 9.5 Programming
      1. 9.5.1 SMBus Interface
        1. 9.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 9.5.1.2 Timing Diagrams
    6. 9.6 Register Map
      1. 9.6.1  Setting Charge and PROCHOT Options
        1. 9.6.1.1 ChargeOption0 Register (SMBus address = 12h) [reset = E70Eh]
        2. 9.6.1.2 ChargeOption1 Register (SMBus address = 30h) [reset = 0211h]
        3. 9.6.1.3 ChargeOption2 Register (SMBus address = 31h) [reset = 02B7h]
        4. 9.6.1.4 ChargeOption3 Register (SMBus address = 32h) [reset = 0030h]
        5. 9.6.1.5 ProchotOption0 Register (SMBus address = 33h) [reset = 4A65h]
        6. 9.6.1.6 ProchotOption1 Register (SMBus address = 34h) [reset = 81A0h]
        7. 9.6.1.7 ADCOption Register (SMBus address = 35h) [reset = 2000h]
      2. 9.6.2  Charge and PROCHOT Status
        1. 9.6.2.1 ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
        2. 9.6.2.2 ProchotStatus Register (SMBus address = 21h) [reset = A800h]
      3. 9.6.3  ChargeCurrent Register (SMBus address = 14h) [reset = 0000h]
        1. 9.6.3.1 Battery Precharge Current Clamp
      4. 9.6.4  MaxChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting]
      5. 9.6.5  MinSystemVoltage Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
        1. 9.6.5.1 System Voltage Regulation
      6. 9.6.6  Input Current and Input Voltage Registers for Dynamic Power Management
        1. 9.6.6.1 Input Current Registers
          1. 9.6.6.1.1 IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4100h]
          2. 9.6.6.1.2 IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) [reset = 4100h]
          3. 9.6.6.1.3 InputVoltage Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
      7. 9.6.7  OTGVoltage Register (SMBus address = 3Bh) [reset = 0000h]
      8. 9.6.8  OTGCurrent Register (SMBus address = 3Ch) [reset = 0000h]
      9. 9.6.9  ADCVBUS/PSYS Register (SMBus address = 23h)
      10. 9.6.10 ADCIBAT Register (SMBus address = 24h)
      11. 9.6.11 ADCIINCMPIN Register (SMBus address = 25h)
      12. 9.6.12 ADCVSYSVBAT Register (SMBus address = 26h)
      13. 9.6.13 ID Registers
        1. 9.6.13.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h]
        2. 9.6.13.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 0h]
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 ACP-ACN Input Filter
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Input Capacitor
        4. 10.2.2.4 Output Capacitor
        5. 10.2.2.5 Power MOSFETs Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
      1. 12.2.1 Layout Example Reference Top View
      2. 12.2.2 Inner Layer Layout and Routing Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Pin Configuration and Functions

GUID-9096E099-811D-4B81-A3C2-E734890E9F03-low.gif Figure 7-1 RSN Package32-Pin WQFNTop View
Table 7-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
ACN 2 PWR Input current sense resistor negative input. The leakage on ACP and ACN are matched. A R-C low-pass filter is required to be placed between the sense resistor and the ACN pin to suppress the high frequency noise in the input current signal. Refer to Section 10 for ACP/ACN filter design.
ACP 3 PWR Input current sense resistor positive input. The leakage on ACP and ACN are matched. A R-C low-pass filter is required to be placed between the sense resistor and the ACP pin to suppress the high frequency noise in the input current signal. Refer to Section 10 for ACP/ACN filter design.
BATDRV 21 O P-channel battery FET (BATFET) gate driver output. It is shorted to VSYS to turn off the BATFET. It goes 10 V below VSYS to fully turn on BATFET. BATFET is in linear mode to regulate VSYS at minimum system voltage when battery is depleted. BATFET is fully on during fast charge and works as an ideal-diode in supplement mode.
BTST1 30 PWR Buck mode high side power MOSFET driver power supply. Connect a 0.047-µF capacitor between SW1 and BTST1. The bootstrap diode between REGN and BTST1 is integrated.
BTST2 25 PWR Boost mode high side power MOSFET driver power supply. Connect a 0.047-μF capacitor between SW2 and BTST2. The bootstrap diode between REGN and BTST2 is integrated.
CELL_BATPRESZ 18 I Battery cell selection pin for 1–4 cell battery setting. CELL_BATPRESZ pin is biased from VDDA. CELL_BATPRESZ pin also sets SYSOVP thresholds to 5 V for 1-cell, 12 V for 2-cell, and 19.5 V for 3-cell/4-cell. CELL_BATPRESZ pin is pulled below VCELL_BATPRESZ_FALL to indicate battery removal. The device exits LEARN mode, and disables charge. The charge voltage register REG0x15() goes back to default.
CHRG_OK 4 O Open drain active high indicator to inform the system good power source is connected to the charger input. Connect to the pullup rail via 10-kΩ resistor. When VBUS rises above 3.5V or falls below 24.5V, CHRG_OK is HIGH after 50ms deglitch time. When VBUS falls below 3.2 V or rises above 26 V, CHRG_OK is LOW. When any fault occurs, CHRG_OK is asserted LOW.
CMPIN 14 I Input of independent comparator. The independent comparator compares the voltage sensed on CMPIN pin with internal reference, and its output is on CMPOUT pin. Internal reference, output polarity and deglitch time is selectable by the SMBus host. With polarity HIGH (REG0x30[6] = 1), place a resistor between CMPIN and CMPOUT to program hysteresis. With polarity LOW (REG0x30[6] = 0), the internal hysteresis is 100 mV. If the independent comparator is not in use, tie CMPIN to ground.
CMPOUT 15 O Open-drain output of independent comparator. Place pullup resistor from CMPOUT to pullup supply rail. Internal reference, output polarity and deglitch time are selectable by the SMBus host.
COMP2 17 I Buck boost converter compensation pin 2. Refer to BQ2571X EVM schematic for COMP2 pin RC network.
COMP1 16 I Buck boost converter compensation pin 1. Refer to BQ2571X EVM schematic for COMP1 pin RC network.
OTG/VAP 5 I Active HIGH to enable OTG or VAP modes. When REG0x32[5]=1, pulling high OTG/VAP pin and setting REG0x32[12]=1 can enable OTG mode. When REG0x32[5]=0, pulling high OTG/VAP pin is to enable VAP mode.
HIDRV1 31 O Buck mode high side power MOSFET (Q1) driver. Connect to high side n-channel MOSFET gate.
HIDRV2 24 O Boost mode high side power MOSFET(Q4) driver. Connect to high side n-channel MOSFET gate.
IADPT 8 O The adapter current monitoring output pin. V(IADPT) = 20 or 40 × (V(ACP) – V(ACN)) with ratio selectable in REG0x12[4]. Place a resistor from the IADPT pin to ground corresponding to the inductance in use. For a 2.2 µH inductance, the resistor is 137 kΩ. Place a 100-pF or less ceramic decoupling capacitor from IADPT pin to ground. IADPT output voltage is clamped below 3.3 V.
IBAT 9 O The battery current monitoring output pin. V(IBAT) = 8 or 16 × (V(SRP) – V(SRN)) for charge current, or V(IBAT) = 8 or 16 × (V(SRN) – V(SRP)) for discharge current, with ratio selectable in REG0x12[3]. Place a 100-pF or less ceramic decoupling capacitor from IBAT pin to ground. This pin can be floating if not in use. Its output voltage is clamped below 3.3 V.
ILIM_HIZ 6 I Input current limit setting pin. Program ILIM_HIZ voltage by connecting a resistor divider from supply rail to ILIM_HIZ pin to ground. The pin voltage is calculated as: V(ILIM_HIZ) = 1 V + 40 × IDPM × RAC, in which IDPM is the target input current. The input current limit used by the charger is the lower setting of ILIM_HIZ pin and REG0x3F(). When the pin voltage is below 0.4 V, the device enters Hi-Z mode with low quiescent current. When the pin voltage is above 0.8 V, the device is out of Hi-Z mode.
LODRV1 29 O Buck mode low side power MOSFET (Q2) driver. Connect to low side n-channel MOSFET gate.
LODRV2 26 O Boost mode low side power MOSFET (Q3) driver. Connect to low side n-channel MOSFET gate.
PGND 27 GND Device power ground.
PROCHOT 11 O Active low open drain output of processor hot indicator. It monitors adapter input current, battery discharge current, and system voltage. After any event in the PROCHOT profile is triggered, a pulse is asserted. The minimum pulse width is adjustable in REG0x21[14:11].
PSYS 10 O Current mode system power monitor. The output current is proportional to the total power from the adapter and the battery. The gain is selectable through SMBus. Place a resistor from PSYS to ground to generate output voltage. This pin can be floating if not in use. Its output voltage is clamped below 3.3 V. Place a capacitor in parallel with the resistor for filtering.
REGN 28 PWR 6-V linear regulator output supplied from VBUS or VSYS. The LDO is active when VBUS above VVBUS_CONVEN. Connect a 2.2- or 3.3-μF ceramic capacitor from REGN to power ground. REGN pin output is for power stage gate drive.
SCL 13 I SMBus clock input. Connect to clock line from the host controller or smart battery. Connect a 10-kΩ pullup resistor according to SMBus specifications.
SDA 12 I/O SMBus open-drain data I/O. Connect to data line from the host controller or smart battery. Connect a 10-kΩ pullup resistor according to SMBus specifications.
SRN 19 PWR Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well. Connect SRN pin with optional 0.1-μF ceramic capacitor to GND for common-mode filtering. Connect a 0.1-μF ceramic capacitor from SRP to SRN to provide differential mode filtering. The leakage current on SRP and SRN are matched.
SRP 20 PWR Charge current sense resistor positive input. Connect SRP pin with optional 0.1-uF ceramic capacitor to GND for common-mode filtering. Connect a 0.1-μF ceramic capacitor from SRP to SRN to provide differential mode filtering. The leakage current on SRP and SRN are matched.
SW1 32 PWR Buck mode high side power MOSFET driver source. Connect to the source of the high side n-channel MOSFET.
SW2 23 PWR Boost mode high side power MOSFET driver source. Connect to the source of the high side n-channel MOSFET.
VBUS 1 PWR Charger input voltage. An input low pass filter of 1Ω and 0.47 µF (minimum) is recommended.
VDDA 7 PWR Internal reference bias pin. Connect a 10-Ω resistor from REGN to VDDA and a 1-μF ceramic capacitor from VDDA to power ground.
VSYS 22 PWR Charger system voltage sensing. The system voltage regulation limit is programmed in REG0x15() and REG0x3E().
Thermal pad – – Exposed pad beneath the IC. Always solder thermal pad to the board, and have vias on the thermal pad plane connecting to power ground planes. It serves as a thermal pad to dissipate the heat.