SLUSD83C june   2018  – may 2023 BQ25713 , BQ25713B

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power-Up from Battery Without DC Source
      2. 9.3.2  Vmin Active Protection (VAP) when Battery only Mode
      3. 9.3.3  Power-Up From DC Source
        1. 9.3.3.1 CHRG_OK Indicator
        2. 9.3.3.2 Input Voltage and Current Limit Setup
        3. 9.3.3.3 Battery Cell Configuration
        4. 9.3.3.4 Device Hi-Z State
      4. 9.3.4  USB On-The-Go (OTG)
      5. 9.3.5  Converter Operation
        1. 9.3.5.1 Inductance Detection Through IADPT Pin
        2. 9.3.5.2 Continuous Conduction Mode (CCM)
        3. 9.3.5.3 Pulse Frequency Modulation (PFM)
      6. 9.3.6  Current and Power Monitor
        1. 9.3.6.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 9.3.6.2 High-Accuracy Power Sense Amplifier (PSYS)
      7. 9.3.7  Input Source Dynamic Power Manage
      8. 9.3.8  Two-Level Adapter Current Limit (Peak Power Mode)
      9. 9.3.9  Processor Hot Indication
        1. 9.3.9.1 PROCHOT During Low Power Mode
        2. 9.3.9.2 PROCHOT Status
      10. 9.3.10 Device Protection
        1. 9.3.10.1 Watchdog Timer
        2. 9.3.10.2 Input Overvoltage Protection (ACOV)
        3. 9.3.10.3 Input Overcurrent Protection (ACOC)
        4. 9.3.10.4 System Overvoltage Protection (SYSOVP)
        5. 9.3.10.5 Battery Overvoltage Protection (BATOVP)
        6. 9.3.10.6 Battery Short
        7. 9.3.10.7 System Short Hiccup Mode
        8. 9.3.10.8 Thermal Shutdown (TSHUT)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Forward Mode
        1. 9.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 9.4.1.2 Battery Charging
      2. 9.4.2 USB On-The-Go
      3. 9.4.3 Pass Through Mode (PTM)
    5. 9.5 Programming
      1. 9.5.1 I2C Serial Interface
        1. 9.5.1.1 Data Validity
        2. 9.5.1.2 START and STOP Conditions
        3. 9.5.1.3 Byte Format
        4. 9.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.5.1.5 Slave Address and Data Direction Bit
        6. 9.5.1.6 Single Read and Write
        7. 9.5.1.7 Multi-Read and Multi-Write
        8. 9.5.1.8 Write 2-Byte I2C Commands
    6. 9.6 Register Map
      1. 9.6.1  Setting Charge and PROCHOT Options
        1. 9.6.1.1 ChargeOption0 Register (I2C address = 01/00h) [reset = E70Eh]
        2. 9.6.1.2 ChargeOption1 Register (I2C address = 31/30h) [reset = 0211h]
        3. 9.6.1.3 ChargeOption2 Register (I2C address = 33/32h) [reset = 02B7h]
        4. 9.6.1.4 ChargeOption3 Register (I2C address = 35/34h) [reset = 0030h]
        5. 9.6.1.5 ProchotOption0 Register (I2C address = 37/36h) [reset = 4A65h]
        6. 9.6.1.6 ProchotOption1 Register (I2C address = 39/38h) [reset = 81A0h]
        7. 9.6.1.7 ADCOption Register (I2C address = 3B/3Ah) [reset = 2000h]
      2. 9.6.2  Charge and PROCHOT Status
        1. 9.6.2.1 ChargerStatus Register (I2C address = 21/20h) [reset = 0000h]
        2. 9.6.2.2 ProchotStatus Register (I2C address = 23/22h) [reset = A800h]
      3. 9.6.3  ChargeCurrent Register (I2C address = 03/02h) [reset = 0000h]
        1. 9.6.3.1 Battery Precharge Current Clamp
      4. 9.6.4  MaxChargeVoltage Register (I2C address = 05/04h) [reset value based on CELL_BATPRESZ pin setting]
      5. 9.6.5  MinSystemVoltage Register (I2C address = 0D/0Ch) [reset value based on CELL_BATPRESZ pin setting]
        1. 9.6.5.1 System Voltage Regulation
      6. 9.6.6  Input Current and Input Voltage Registers for Dynamic Power Management
        1. 9.6.6.1 Input Current Registers
          1. 9.6.6.1.1 IIN_HOST Register With 10-mΩ Sense Resistor (I2C address = 0F/0Eh) [reset = 4100h]
          2. 9.6.6.1.2 IIN_DPM Register With 10-mΩ Sense Resistor (I2C address = 25/24h) [reset = 4100h]
          3. 9.6.6.1.3 InputVoltage Register (I2C address = 0B/0Ah) [reset = VBUS-1.28V]
      7. 9.6.7  OTGVoltage Register (I2C address = 07/06h) [reset = 0000h]
      8. 9.6.8  OTGCurrent Register (I2C address = 09/08h) [reset = 0000h]
      9. 9.6.9  ADCVBUS/PSYS Register (I2C address = 27/26h)
      10. 9.6.10 ADCIBAT Register (I2C address = 29/28h)
      11. 9.6.11 ADCIINCMPIN Register (I2C address = 2B/2Ah)
      12. 9.6.12 ADCVSYSVBAT Register (I2C address = 2D/2Ch)
      13. 9.6.13 ID Registers
        1. 9.6.13.1 ManufactureID Register (I2C address = 2Eh) [reset = 0040h]
        2. 9.6.13.2 Device ID (DeviceAddress) Register (I2C address = 2Fh) [reset = 0h]
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 ACP-ACN Input Filter
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Input Capacitor
        4. 10.2.2.4 Output Capacitor
        5. 10.2.2.5 Power MOSFETs Selection
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
      1. 12.2.1 Layout Example Reference Top View
      2. 12.2.2 Inner Layer Layout and Routing Example
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 Electrical Characteristics

over TJ = -40°C to 125°C (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VINPUT_OPInput voltage operating range3.526V
REGULATION ACCURACY
MAX SYSTEM VOLTAGE REGULATION
VSYSMAX_RNGSystem Voltage Regulation, measured on VSYS (charge disabled)1.02419.2V
VSYSMAX_ACCSystem voltage regulation accuracy (charge disabled)REG0x05/04() = 0x41A0H (16.800 V)VSRN + 160 mVV
–2%2%
REG0x05/04() = 0x3138H (12.600 V)VSRN + 160 mVV
–2%2%
REG0x05/04() = 0x20D0H (8.400 V)VSRN + 160 mVV
–3%3%
REG0x05/04() = 0x1068H (4.200 V)VSRN + 160 mVV
–3%3%
MINIMUM SYSTEM VOLTAGE REGULATION
VSYSMIN_RNGSystem Voltage Regulation, measured on VSYS1.02419.2V
VSYSMIN_REG_ACCMinimum System Voltage Regulation Accuracy (VBAT below REG0x0D/0C() setting)REG0x0D/0C() = 0x3000H12.288V
–2%2%
REG0x0D/0C() = 0x2400H9.216V
–2%2%
REG0x0D/0C() = 0x1800H6.144V
–3%3%
REG0x0D/0C() = 0x0E00H3.584V
–3%3%
CHARGE VOLTAGE REGULATION
VBAT_RNGBattery voltage regulation1.02419.2V
VBAT_REG_ACCBattery voltage regulation accuracy (charge enable) (0°C to 85°C)REG0x05/04() = 0x41A0H16.8V
–0.5%0.5%
REG0x05/04() = 0x3138H12.6V
–0.5%0.5%
REG0x05/04() = 0x20D0H8.4V
–0.6%0.6%
REG0x05/04() = 0x1068H4.2V
–1.1%1.2%
CHARGE CURRENT REGULATION IN FAST CHARGE
VIREG_CHG_RNGCharge current regulation differential voltage rangeVIREG_CHG = VSRP –VSRN081.28mV
ICHRG_REG_ACCCharge current regulation accuracy 10-mΩ sensing resistor, VBAT above REG0x0D/0C() setting (0°C to 85°C)REG0x03/02() = 0x1000H4096mA
–3%2%
REG0x03/02() = 0x0800H2048mA
–4%3%
REG0x03/02() = 0x0400H1024mA
–5%6%
REG0x03/02() = 0x0200H512mA
–12%12%
CHARGE CURRENT REGULATION IN LDO MODE
ICLAMPPrecharge current clampCELL 2s-4s384mA
CELL 1 s, VSRN < 3 V384mA
CELL 1 s, 3 V < VSRN < VSYSMIN2A
IPRECHRG_REG_ACCPrecharge current regulation accuracy with 10-mΩ SRP/SRN series resistor, VBAT below REG0x0D/0C() setting (0°C to 85°C)REG0x03/02() = 0x0180H384mA
2S-4S–15%15%
1S–25%25%
REG0x03/02() = 0x0100H256mA
2S-4S–20%20%
1S–35%35%
REG0x03/02() = 0x00C0H192mA
2S-4S–25%25%
1S–50%50%
REG0x03/02() = 0x0080H128mA
2S-4S–30%30%
ILEAK_SRP_SRNSRP, SRN leakage current mismatch (0°C to 85°C)–1210µA
INPUT CURRENT REGULATION
VIREG_DPM_RNGInput current regulation differential voltage rangeVIREG_DPM = VACP – VACN0.564mV
IDPM_REG_ACCInput current regulation accuracy (-40°C to 105°C) with 10-mΩ ACP/ACN series resistorREG0x0F/0E() = 0x5000H380039004000mA
REG0x0F/0E() = 0x3C00H280029003000mA
REG0x0F/0E() = 0x1E00H130014001500mA
REG0x0F/0E() = 0x0A00H300400500mA
ILEAK_ACP_ACNACP, ACN leakage current mismatch (-40°C to 105°C)–1610µA
VIREG_DPM_RNG_ILIMVoltage range for input current regulation (ILIM_HIZ Pin)1.154V
IDPM_REG_ACC_ILIMInput Current Regulation Accuracy on ILIM_HIZ pin VILIM_HIZ = 1 V + 40 × IDPM × RAC, with 10-mΩ ACP/ACN series resistorVILIM_HIZ = 2.6 V380040004200mA
VILIM_HIZ = 2.2 V280030003200mA
VILIM_HIZ = 1.6 V130015001700mA
VILIM_HIZ = 1.2 V300500700mA
ILEAK_ILIMILIM_HIZ pin leakage current–11µA
INPUT VOLTAGE REGULATION
VIREG_DPM_RNGInput voltage regulation rangeVoltage on VBUS3.219.52V
VDPM_REG_ACCInput voltage regulation accuracyREG0x0B/0A()=0x3C80H18688mV
–3%2%
REG0x0B/0A()=0x1E00H10880mV
–4%2.5%
REG0x0B/0A()=0x0500H4480mV
–5%5%
OTG CURRENT REGULATION
VIOTG_REG_RNGOTG output current regulation differential voltage rangeVIOTG_REG = VACP – VACN081.28mV
IOTG_ACCOTG output current regulation accuracy with 50-mA LSB and 10-mΩ ACP/ACN series resistorREG0x09/08() = 0x3C00H280030003200mA
REG0x09/08() = 0x1E00H130015001700mA
REG0x09/08() = 0x0A00H300500700mA
OTG VOLTAGE REGULATION
VOTG_REG_RNGOTG voltage regulation rangeVoltage on VBUS320.8V
VOTG_REG_ACCOTG voltage regulation accuracyREG0x07/06() = 0x23F8H

REG0x34[2] = 0

20.002V
–2%2%
REG0x07/06() = 0x1710H

REG0x34[2] = 1

12.004V
–2%2%
REG0x07/06() = 0x099CH

REG0x34[2] = 1

5.002V
–3%3%
REFERENCE AND BUFFER
REGN REGULATOR
VREGN_REGREGN regulator voltage (0 mA – 60 mA)VVBUS = 10 V5.766.3V
VDROPOUTREGN voltage in drop out modeVVBUS = 5 V, ILOAD = 20 mA3.84.34.6V
IREGN_LIM_ChargingREGN current limit when converter is enabledVVBUS = 10 V, force VREGN =4 V5065mA
CREGNREGN output capacitor required for stabilityILOAD = 100 µA to 50 mA2.2µF
CVDDAREGN output capacitor required for stabilityILOAD = 100 µA to 50 mA1µF
QUIESCENT CURRENT
IBAT_BATFET_ONSystem powered by battery. BATFET on. ISRN + ISRP + ISW2 + IBTST2 + ISW1 + IBTST1 + IACP + IACN + IVBUS + IVSYSVBAT = 18 V, REG0x01[7] = 1, in low power mode2245µA
VBAT = 18 V, REG0x01[7] = 1, REG0x31[5] = 1, REGN off125195µA
VBAT = 18 V, REG0x01[7] = 0, REG0x31[4] = 0, REGN on, DIS_PSYS8801170µA
VBAT = 18 V, REG0x01[7] = 0, REG0x31[4] = 1, REGN on, EN_PSYS9801270µA
IAC_SW_LIGHT_buckInput current during PFM in buck mode, no load, IVBUS + IACP + IACN + IVSYS + ISRP + ISRN + ISW1 + IBTST + ISW2 + IBTST2VIN = 20 V, VBAT = 12.6 V, 3s, REG0x01[2] = 0; MOSFET Qg = 4 nC2.2mA
IAC_SW_LIGHT_boostInput current during PFM in boost mode, no load, IVBUS + IACP + IACN + IVSYS + ISRP + ISRN + ISW1 + IBTST2 + ISW2 + IBTST2VIN = 5 V, VBAT = 8.4 V, 2s, REG0x01[2] = 0; MOSFET Qg = 4 nC2.7mA
IAC_SW_LIGHT_buckboostInput current during PFM in buck boost mode, no load, IVBUS + IACP + IACN + IVSYS + ISRP + ISRN + ISW1 + IBTST1 + ISW2 + IBTST2VIN = 12 V, VBAT = 12 V, REG0x01[2] = 0; MOSFET Qg = 4 nC2.4mA
IOTG_STANDBYQuiescent current during PFM in OTG mode IVBUS + IACP + IACN + IVSYS + ISRP + ISRN + ISW1 + IBTST2 + ISW2 + IBTST2VBAT = 8.4 V, VBUS = 5 V, 800 kHz switching frequency, MOSFET Qg = 4nC3mA
VBAT = 8.4 V, VBUS = 12 V, 800 kHz switching frequency, MOSFET Qg = 4nC4.2mA
VBAT = 8.4 V, VBUS = 20 V, 800 kHz switching frequency, MOSFET Qg = 4nC6.2mA
VACP/N_OPInput common mode rangeVoltage on ACP/ACN3.826V
VIADPT_CLAMPIADPT output clamp voltage3.13.23.3V
IIADPTIADPT output current1mA
AIADPTInput current sensing gainV(IADPT) / V(ACP-ACN), REG0x00[4] = 020V/V
V(IADPT) / V(ACP-ACN), REG0x00[4] = 140V/V
VIADPT_ACCInput current monitor accuracyV(ACP-ACN) = 40.96 mV–2%2%
V(ACP-ACN) = 20.48 mV–3%3%
V(ACP-ACN) =10.24 mV–6%6%
V(ACP-ACN) = 5.12 mV–10%10%
CIADPT_MAXMaximum capacitance at IADPT Pin100pF
VSRP/N_OPBattery common mode rangeVoltage on SRP/SRN2.518V
VIBAT_CLAMPIBAT output clamp voltage3.053.23.3V
IIBATIBAT output current1mA
AIBATCharge and discharge current sensing gain on IBAT pinV(IBAT) / V(SRN-SRP), REG0x00[3] = 0,8V/V
V(IBAT) / V(SRN-SRP), REG0x00[3] = 1,16V/V
IIBAT_CHG_ACCCharge and discharge current monitor accuracy on IBAT pinV(SRN-SRP) = 40.96 mV–2%2%
V(SRN-SRP) = 20.48 mV–4%4%
V(SRN-SRP) =10.24 mV–7%7%
V(SRN-SRP) = 5.12 mV–15%15%
CIBAT_MAXMaximum capacitance at IBAT Pin100pF
SYSTEM POWER SENSE AMPLIFIER
VPSYSPSYS output voltage range03.3V
IPSYSPSYS output current0160µA
APSYSPSYS system gainV(PSYS) / (P(IN) +P(BAT)), REG0x31[1] = 11µA/W
VPSYS_ACCPSYS gain accuracy (REG0x31[1] = 1)Adapter only with system power = 19.5 V / 45 W, TA = -40°C to 85°C–4%4%
Battery only with system power = 11 V / 44 W, TA = –40°C to 85°C–3%3%
VPSYS_CLAMPPSYS clamp voltage33.3V
COMPARATOR
VBUS UNDER VOLTAGE LOCKOUT COMPARATOR
VVBUS_UVLOZVBUS undervoltage rising thresholdVBUS rising2.302.552.80V
VVBUS_UVLOVBUS undervoltage falling thresholdVBUS falling2.182.402.62V
VVBUS_UVLO_HYSTVBUS undervoltage hysteresis150mV
VVBUS_CONVENVBUS converter enable rising thresholdVBUS rising3.23.53.9V
VVBUS_CONVENZVBUS converter enable falling thresholdVBUS falling2.93.23.5V
VVBUS_CONVEN_HYSTVBUS converter enable hysteresis400mV
BATTERY UNDER VOLTAGE LOCKOUT COMPARATOR
VVBAT_UVLOZVBAT undervoltage rising thresholdVSRN rising2.352.552.75V
VVBAT_UVLOVBAT undervoltage falling thresholdVSRN falling2.22.42.6V
VVBAT_UVLO_HYSTVBAT undervoltage hysteresis150mV
VVBAT_OTGENVBAT OTG enable rising thresholdVSRN rising3.253.553.85V
VVBAT_OTGENZVBAT OTG enable falling thresholdVSRN falling2.22.42.6V
VVBAT_OTGEN_HYSTVBAT OTG enable hysteresis1100mV
VBUS UNDER VOLTAGE COMPARATOR (OTG MODE)
VVBUS_OTG_UVVBUS undervoltage falling thresholdAs percentage of REG0x07/06()85%
tVBUS_OTG_UVVBUS time undervoltage deglitch7ms
VBUS OVER VOLTAGE COMPARATOR (OTG MODE)
VVBUS_OTG_OVVBUS overvoltage rising thresholdAs percentage of REG0x07/06()110%
tVBUS_OTG_OVVBUS Time Over-Voltage Deglitch10ms
PRECHARGE to FAST CHARGE TRANSITION
VBAT_SYSMIN_RISELDO mode to fast charge mode threshold, VSRN risingas percentage of 0x0D/0C()98100102%
VBAT_SYSMIN_FALLLDO mode to fast charge mode threshold, VSRN fallingas percentage of 0x0D/0C()97.5%
VBAT_SYSMIN_HYSTFast charge mode to LDO mode threshold hysteresisas percentage of 0x0D/0C()2.5%
BATTERY LOWV COMPARATOR (Precharge to Fast Charge Threshold for 1S)
VBATLV_FALLBATLOWV falling threshold1 s2.8V
VBATLV_RISEBATLOWV rising threshold3V
VBATLV_RHYSTBATLOWV hysteresis200mV
INPUT OVER-VOLTAGE COMPARATOR (ACOVP)
VACOV_RISEVBUS overvoltage rising thresholdVBUS rising252627V
VACOV_FALLVBUS overvoltage falling thresholdVBUS falling23.524.525V
VACOV_HYSTVBUS overvoltage hysteresis1.5V
tACOV_RISE_DEGVBUS deglitch overvoltage risingVBUS converter rising to stop converter100µs
tACOV_FALL_DEGVBUS deglitch overvoltage fallingVBUS converter falling to start converter1ms
INPUT OVER CURRENT COMPARATOR (ACOC)
VACOCACP to ACN rising threshold, w.r.t. ILIM2 in REG0x37[7:4]Voltage across input sense resistor rising, REG0x32[2] = 11.822.2
VACOC_FLOORMeasure between ACP and ACNSet IDPM to minimum445056mV
VACOC_CEILINGMeasure between ACP and ACNSet IDPM to maximum172180188mV
tACOC_DEG_RISERising deglitch timeDeglitch time to trigger ACOC250µs
tACOC_RELAXRelax timeRelax time before converter starts again250ms
SYSTEM OVER-VOLTAGE COMPARATOR (SYSOVP)
VSYSOVP_RISESystem overvoltage rising threshold to turn off converter1 s4.8555.1V
2 s11.71212.2V
3 s, 4 s1919.520V
VSYSOVP_FALLSystem overvoltage falling threshold1 s4.8V
2 s11.5V
3 s, 4 s19V
ISYSOVPDischarge current when SYSOVP stop switching was triggeredon SYS20mA
BAT OVER-VOLTAGE COMPARATOR (BATOVP)
VBATOVP_RISEOvervoltage rising threshold as percentage of VBAT_REG in REG0x05/04()1 s, 4.2 V102.5104106%
2 s - 4 s102.5104105%
VBATOVP_FALLOvervoltage falling threshold as percentage of VBAT_REG in REG0x05/04()1 s100102104%
2 s - 4 s100102103%
VBATOVP_HYSTOvervoltage hysteresis as percentage of VBAT_REG in REG0x05/04()1 s2%
2 s - 4 s2%
IBATOVPDischarge current during BATOVPon VSYS pin20mA
tBATOVP_RISEOvervoltage rising deglitch to turn off BATDRV to disable charge20ms
CONVERTER OVER-CURRENT COMPARATOR (Q2)
VOCP_limit_Q2Converter Over-Current LimitREG0x32[5]=1150mV
REG0x32[5]=0210mV
VOCP_limit_SYSSHORT_Q2System Short or SRN < 2.4 VREG0x32[5]=145mV
REG0x32[5]=060mV
CONVERTER OVER-CURRENT COMPARATOR (ACX)
VOCP_limit_ACXConverter Over-Current LimitREG0x32[4]=1150mV
REG0x32[4]=0280mV
VOCP_limit_SYSSHORT_ACXSystem Short or SRN < 2.4 VREG0x32[4]=190mV
REG0x32[4]=0150mV
THERMAL SHUTDOWN COMPARATOR
TSHUT_RISEThermal shutdown rising temperatureTemperature increasing155°C
TSHUTF_FALLThermal shutdown falling temperatureTemperature reducing135°C
TSHUT_HYSThermal shutdown hysteresis20°C
tSHUT_RDEGThermal deglitch shutdown rising100µs
tSHUT_FHYSThermal deglitch shutdown falling12ms
VSYS PROCHOT COMPARATOR
VSYS_TH1VSYS_TH1 comparator falling thresholdREG0x36[7:4] = 0111, 2-4 s6.6V
REG0x36[7:4] = 0100, 1 s3.5V
VSYS_TH2VSYS_TH2 comparator falling thresholdREG0x36[3:2] = 10, 2-4 s6.5V
REG0x36[3:2] = 10, 1 s3.5V
tSYS_PRO_falling_DEGVSYS falling deglitch for throttling4µs
ICRIT PROCHOT COMPARATOR
VICRIT_PROInput current rising threshold for throttling as 10% above ILIM2 (REG0x37[7:3])Only when ILIM2 setting is higher than 2A105110117%
INOM PROCHOT COMPARATOR
VINOM_PROINOM rising threshold as 10% above IIN (REG0x0F/0E())105110116%
IDCHG PROCHOT COMPARATOR
VIDCHG_PROIDCHG threshold for throttling for IDSCHG of 6 AREG0x39[7:2] = 0011006272mA
95103%
INDEPENDENT COMPARATOR
VINDEP_CMPIndependent comparator thresholdREG0x30[7] = 1, CMPIN falling1.171.21.23V
REG0x30[7] = 0, CMPIN falling2.272.32.33V
VINDEP_CMP_HYSIndependent comparator hysteresisREG0x30[7] = 0, CMPIN falling100mV
POWER MOSFET DRIVER
PWM OSCILLATOR AND RAMP
FSWPWM switching frequencyREG0x01[1] = 0102012001380kHz
REG0x01[1] = 1680800920kHz
BATFET GATE DRIVER (BATDRV)
VBATDRV_ONGate drive voltage on BATFET8.51011.5V
VBATDRV_DIODEDrain-source voltage on BATFET during ideal diode operation30mV
RBATDRV_ONMeasured by sourcing 10 µA current to BATDRV2.546kΩ
RBATDRV_OFFMeasured by sinking 10 µA current from BATDRV1.22.1kΩ
PWM HIGH SIDE DRIVER (HIDRV Q1)
RDS_HI_ON_Q1High side driver (HSD) turn on resistanceVBTST1 - VSW1 = 5 V6Ω
RDS_HI_OFF_Q1High side driver turn off resistanceVBTST1 - VSW1 = 5 V1.32.2Ω
VBTST1_REFRESHBootstrap refresh comparator falling threshold voltageVBTST1 - VSW1 when low side refresh pulse is requested3.23.74.6V
PWM HIGH SIDE DRIVER (HIDRV Q4)
RDS_HI_ON_Q4High side driver (HSD) turn on resistanceVBTST2 - VSW2 = 5 V6Ω
RDS_HI_OFF_Q4High side driver turn off resistanceVBTST2 - VSW2 = 5 V1.52.4Ω
VBTST2_REFRESHBootstrap refresh comparator falling threshold voltageVBTST2 - VSW2 when low side refresh pulse is requested3.13.74.5V
PWM LOW SIDE DRIVER (LODRV Q2)
RDS_LO_ON_Q2Low side driver (LSD) turn on resistanceVBTST1 - VSW1 = 5.5 V6Ω
RDS_LO_OFF_Q2Low side driver turn off resistanceVBTST1 - VSW1 = 5.5 V1.72.6Ω
PWM LOW SIDE DRIVER (LODRV Q3)
RDS_LO_ON_Q3Low side driver (LSD) turn on resistanceVBTST2 - VSW2 = 5.5 V7.6Ω
RDS_LO_OFF_Q3Low side driver turn off resistanceVBTST2 - VSW2 = 5.5 V2.94.6Ω
INTERNAL SOFT START During Charge Enable
SSSTEP_DACSoft Start Step Size64mA
SSSTEP_DACSoft Start Step Time8µs
INTEGRATED BTST DIODE (D1)
VF_D1Forward bias voltageIF = 20 mA at 25°C0.8V
VR_D1Reverse breakdown voltageIR = 2 µA at 25°C20V
INTEGRATED BTST DIODE (D2)
VF_D2Forward bias voltageIF = 20 mA at 25°C0.8V
VR_D2Reverse breakdown voltageIR = 2 µA at 25°C20V
INTERFACE
LOGIC INPUT (SDA, SCL, OTG/VAP)
VIN_ LOInput low thresholdI2C0.4V
VIN_ HIInput high thresholdI2C1.3V
LOGIC OUTPUT OPEN DRAIN (SDA, CHRG_OK, CMPOUT)
VOUT_ LOOutput saturation voltage5 mA drain current0.4V
VOUT_ LEAKLeakage currentV = 7 V–11µA
LOGIC OUTPUT OPEN DRAIN SDA
VOUT_ LO_SDAOutput Saturation Voltage5 mA drain current0.4V
VOUT_ LEAK_SDALeakage CurrentV = 7V–11µA
LOGIC OUTPUT OPEN DRAIN CHRG_OK
VOUT_ LO_CHRG_OKOutput Saturation Voltage5 mA drain current0.4V
VOUT_ LEAK _CHRG_OKLeakage CurrentV = 7V–11µA
LOGIC OUTPUT OPEN DRAIN CMPOUT
VOUT_ LO_CMPOUTOutput Saturation Voltage5 mA drain current0.4V
VOUT_ LEAK _CMPOUTLeakage CurrentV = 7V–11µA
LOGIC OUTPUT OPEN DRAIN (PROCHOT)
VOUT_ LO_PROCHOTOutput saturation voltage50 Ω pullup to 1.05 V / 5-mA300mV
VOUT_ LEAK_PROCHOTLeakage currentV = 5.5 V–11µA
ANALOG INPUT (ILIM_HIZ)
VHIZ_ LOVoltage to get out of HIZ modeILIM_HIZ pin rising0.8V
VHIZ_ HIGHVoltage to enable HIZ modeILIM_HIZ pin falling0.4V
ANALOG INPUT (CELL_BATPRESZ)
VCELL_4S4SREGN of REGN = 6 V, as percentage68.475%
VCELL_3S3SREGN of REGN = 6 V, as percentage51.75565%
VCELL_2S2SREGN of REGN = 6 V, as percentage354049.1%
VCELL_1S1SREGN of REGN = 6 V, as percentage18.42531.6%
VCELL_BATPRESZ_RISEBattery is presentCELL_BATPRESZ rising18%
VCELL_BATPRESZ_FALLBattery is removedCELL_BATPRESZ falling15%