SLUSDU3
May 2021
BQ25720
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Description (continued)
6
Device Comparison Table
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Timing Requirements
8.7
Typical Characteristics
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Power-Up Sequence
9.3.2
Vmin Active Protection (VAP) with Battery only
9.3.3
Two-Level Battery Discharge Current Limit
9.3.4
Fast Role Swap Feature
9.3.5
CHRG_OK Indicator
9.3.6
Input and Charge Current Sensing
9.3.7
Input Voltage and Current Limit Setup
9.3.8
Battery Cell Configuration
9.3.9
Device HIZ State
9.3.10
USB On-The-Go (OTG)
9.3.11
Converter Operation
9.3.12
Inductance Detection Through IADPT Pin
9.3.13
Converter Compensation
9.3.14
Continuous Conduction Mode (CCM)
9.3.15
Pulse Frequency Modulation (PFM)
9.3.16
Switching Frequency and Dithering Feature
9.3.17
Current and Power Monitor
9.3.17.1
High-Accuracy Current Sense Amplifier (IADPT and IBAT)
9.3.17.2
High-Accuracy Power Sense Amplifier (PSYS)
9.3.18
Input Source Dynamic Power Management
9.3.19
Input Current Optimizer (ICO)
9.3.20
Two-Level Adapter Current Limit (Peak Power Mode)
9.3.21
Processor Hot Indication
9.3.21.1
PROCHOT During Low Power Mode
9.3.21.2
PROCHOT Status
9.3.22
Device Protection
9.3.22.1
Watchdog Timer
9.3.22.2
Input Overvoltage Protection (ACOV)
9.3.22.3
Input Overcurrent Protection (ACOC)
9.3.22.4
System Overvoltage Protection (SYSOVP)
9.3.22.5
Battery Overvoltage Protection (BATOVP)
9.3.22.6
Battery Discharge Overcurrent Protection (BATOC)
9.3.22.7
Battery Short Protection (BATSP)
9.3.22.8
System Undervoltage Lockout (VSYS_UVP) and Hiccup Mode
9.3.22.9
Thermal Shutdown (TSHUT)
9.4
Device Functional Modes
9.4.1
Forward Mode
9.4.1.1
System Voltage Regulation with Narrow VDC Architecture
9.4.1.2
Battery Charging
9.4.2
USB On-The-Go
9.4.3
Pass Through Mode (PTM)-Patented Technology
9.5
Programming
9.5.1
SMBus Interface
9.5.1.1
SMBus Write-Word and Read-Word Protocols
9.5.1.2
Timing Diagrams
9.6
Register Map
9.6.1
ChargeOption0 Register (SMBus address = 12h) [reset = E70Eh]
9.6.2
ChargeCurrent Register (SMBus address = 14h) [reset = 0000h]
9.6.2.1
Battery Pre-Charge Current Clamp
9.6.3
ChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting]
9.6.4
ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
9.6.5
ProchotStatus Register (SMBus address = 21h) [reset = B800h]
9.6.6
IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 22h) [reset = 4100h]
9.6.7
ADCVBUS/PSYS Register (SMBus address = 23h)
9.6.8
ADCIBAT Register (SMBus address = 24h)
9.6.9
ADCIINCMPIN Register (SMBus address = 25h)
9.6.10
ADCVSYSVBAT Register (SMBus address = 26h)
9.6.11
ChargeOption1 Register (SMBus address = 30h) [reset = 3300h]
9.6.12
ChargeOption2 Register (SMBus address = 31h) [reset = 00B7]
9.6.13
ChargeOption3 Register (SMBus address = 32h) [reset = 0434h]
9.6.14
ProchotOption0 Register (SMBus address = 33h) [reset = 4A81h(2S~) 4A09(1S)]
9.6.15
ProchotOption1 Register (SMBus address = 34h) [reset = 41A0h]
9.6.16
ADCOption Register (SMBus address = 35h) [reset = 2000h]
9.6.17
ChargeOption4 Register (SMBus address = 36h) [reset = 0048h]
9.6.18
Vmin Active Protection Register (SMBus address = 37h) [reset = 006Ch(2s~4s)/0004h(1s)]
9.6.19
OTGVoltage Register (SMBus address = 3Bh) [reset = 09C4h]
9.6.20
OTGCurrent Register (SMBus address = 3Ch) [reset = 3C00h]
9.6.21
InputVoltage (VINDPM) Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
9.6.22
VSYS_MIN Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
9.6.23
IIN_HOST Register (SMBus address = 3Fh) [reset = 4100h]
9.6.24
ID Registers
9.6.24.1
ManufactureID Register (SMBus address = FEh) [reset = 0040h]
9.6.24.2
Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 00E1h]
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
ACP-ACN Input Filter
10.2.2.2
Inductor Selection
10.2.2.3
Input Capacitor
10.2.2.4
Output Capacitor
10.2.2.5
Power MOSFETs Selection
10.2.3
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
12.2.1
Layout Example Reference Top View
12.2.2
Inner Layer Layout and Routing Example
13
Device and Documentation Support
13.1
Device Support
13.1.1
Third-Party Products Disclaimer
13.2
Documentation Support
13.2.1
Related Documentation
13.3
Receiving Notification of Documentation Updates
13.4
Support Resources
13.5
Trademarks
13.6
Electrostatic Discharge Caution
13.7
Glossary
14
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RSN|32
MPQF194B
Thermal pad, mechanical data (Package|Pins)
RSN|32
QFND189E
Orderable Information
slusdu3_oa
slusdu3_pm
10.2
Typical Application
Figure 10-1
Application Diagram of BQ25720