SLUSDU3 May   2021 BQ25720

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power-Up Sequence
      2. 9.3.2  Vmin Active Protection (VAP) with Battery only
      3. 9.3.3  Two-Level Battery Discharge Current Limit
      4. 9.3.4  Fast Role Swap Feature
      5. 9.3.5  CHRG_OK Indicator
      6. 9.3.6  Input and Charge Current Sensing
      7. 9.3.7  Input Voltage and Current Limit Setup
      8. 9.3.8  Battery Cell Configuration
      9. 9.3.9  Device HIZ State
      10. 9.3.10 USB On-The-Go (OTG)
      11. 9.3.11 Converter Operation
      12. 9.3.12 Inductance Detection Through IADPT Pin
      13. 9.3.13 Converter Compensation
      14. 9.3.14 Continuous Conduction Mode (CCM)
      15. 9.3.15 Pulse Frequency Modulation (PFM)
      16. 9.3.16 Switching Frequency and Dithering Feature
      17. 9.3.17 Current and Power Monitor
        1. 9.3.17.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 9.3.17.2 High-Accuracy Power Sense Amplifier (PSYS)
      18. 9.3.18 Input Source Dynamic Power Management
      19. 9.3.19 Input Current Optimizer (ICO)
      20. 9.3.20 Two-Level Adapter Current Limit (Peak Power Mode)
      21. 9.3.21 Processor Hot Indication
        1. 9.3.21.1 PROCHOT During Low Power Mode
        2. 9.3.21.2 PROCHOT Status
      22. 9.3.22 Device Protection
        1. 9.3.22.1 Watchdog Timer
        2. 9.3.22.2 Input Overvoltage Protection (ACOV)
        3. 9.3.22.3 Input Overcurrent Protection (ACOC)
        4. 9.3.22.4 System Overvoltage Protection (SYSOVP)
        5. 9.3.22.5 Battery Overvoltage Protection (BATOVP)
        6. 9.3.22.6 Battery Discharge Overcurrent Protection (BATOC)
        7. 9.3.22.7 Battery Short Protection (BATSP)
        8. 9.3.22.8 System Undervoltage Lockout (VSYS_UVP) and Hiccup Mode
        9. 9.3.22.9 Thermal Shutdown (TSHUT)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Forward Mode
        1. 9.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 9.4.1.2 Battery Charging
      2. 9.4.2 USB On-The-Go
      3. 9.4.3 Pass Through Mode (PTM)-Patented Technology
    5. 9.5 Programming
      1. 9.5.1 SMBus Interface
        1. 9.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 9.5.1.2 Timing Diagrams
    6. 9.6 Register Map
      1. 9.6.1  ChargeOption0 Register (SMBus address = 12h) [reset = E70Eh]
      2. 9.6.2  ChargeCurrent Register (SMBus address = 14h) [reset = 0000h]
        1. 9.6.2.1 Battery Pre-Charge Current Clamp
      3. 9.6.3  ChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting]
      4. 9.6.4  ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
      5. 9.6.5  ProchotStatus Register (SMBus address = 21h) [reset = B800h]
      6. 9.6.6  IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 22h) [reset = 4100h]
      7. 9.6.7  ADCVBUS/PSYS Register (SMBus address = 23h)
      8. 9.6.8  ADCIBAT Register (SMBus address = 24h)
      9. 9.6.9  ADCIINCMPIN Register (SMBus address = 25h)
      10. 9.6.10 ADCVSYSVBAT Register (SMBus address = 26h)
      11. 9.6.11 ChargeOption1 Register (SMBus address = 30h) [reset = 3300h]
      12. 9.6.12 ChargeOption2 Register (SMBus address = 31h) [reset = 00B7]
      13. 9.6.13 ChargeOption3 Register (SMBus address = 32h) [reset = 0434h]
      14. 9.6.14 ProchotOption0 Register (SMBus address = 33h) [reset = 4A81h(2S~) 4A09(1S)]
      15. 9.6.15 ProchotOption1 Register (SMBus address = 34h) [reset = 41A0h]
      16. 9.6.16 ADCOption Register (SMBus address = 35h) [reset = 2000h]
      17. 9.6.17 ChargeOption4 Register (SMBus address = 36h) [reset = 0048h]
      18. 9.6.18 Vmin Active Protection Register (SMBus address = 37h) [reset = 006Ch(2s~4s)/0004h(1s)]
      19. 9.6.19 OTGVoltage Register (SMBus address = 3Bh) [reset = 09C4h]
      20. 9.6.20 OTGCurrent Register (SMBus address = 3Ch) [reset = 3C00h]
      21. 9.6.21 InputVoltage (VINDPM) Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
      22. 9.6.22 VSYS_MIN Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
      23. 9.6.23 IIN_HOST Register (SMBus address = 3Fh) [reset = 4100h]
      24. 9.6.24 ID Registers
        1. 9.6.24.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h]
        2. 9.6.24.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 00E1h]
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 ACP-ACN Input Filter
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Input Capacitor
        4. 10.2.2.4 Output Capacitor
        5. 10.2.2.5 Power MOSFETs Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
      1. 12.2.1 Layout Example Reference Top View
      2. 12.2.2 Inner Layer Layout and Routing Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.6.1 ChargeOption0 Register (SMBus address = 12h) [reset = E70Eh]

Figure 9-8 ChargeOption0 Register (SMBus address = 12h) [reset = E70Eh]
15 14 13 12 11 10 9 8
EN_LWPWR WDTMR_ADJ IIN_DPM_AUTO_DISABLE OTG_ON_CHRGOK EN_OOA PWM_FREQ DIS_STRGRV
R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
EN_CMP_LATCH VSYS_UVP_ENZ EN_LEARN IADPT_GAIN IBAT_GAIN EN_LDO EN_IIN_DPM CHRG_INHIBIT
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-10 ChargeOption0 Register (SMBus address = 12h) Field Descriptions
SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
15 EN_LWPWR R/W 1b

Low Power Mode Enable, under low power mode lowest quiescent current is achieved when only battery exist. It is not recommended to enable low power mode when adapter present.

0b: Disable Low Power Mode. Device in performance mode with battery only. The PROCHOT, current/power monitor buffer and comparator follow register setting.

1b: Enable Low Power Mode. Device in low power mode with battery only for lowest quiescent current. The REGN is off. The PROCHOT, discharge current monitor buffer, power monitor buffer and independent comparator are disabled. ADC is not available in Low Power Mode. Independent comparator and its low power mode PROCHOT profile can be enabled by setting EN_PROCHOT_LPWR bit to 1b. <default at POR>
14-13 WDTMR_ADJ R/W 11b

WATCHDOG Timer Adjust

Set maximum delay between consecutive SMBus write of charge voltage or charge current command.

If device does not receive a write on the REG0x15() or the REG0x14() within the watchdog time period, the charger will be suspended by setting the REG0x14() to 0 mA .

After expiration, the timer will resume upon the write of REG0x14(), REG0x15() or REG0x12[14:13].

00b: Disable Watchdog Timer

01b: Enabled, 5 sec

10b: Enabled, 88 sec

11b: Enable Watchdog Timer, 175 sec <default at POR>
12 IIN_DPM_AUTO_DISABLE R/W 0b

IIN_DPM Auto Disable

When CELL_BATPRESZ pin is LOW, the charger automatically disables the IIN_DPM function by setting EN_IIN_DPM (REG0x12[1]) to 0. The host can enable IIN_DPM function later by writing EN_IIN_DPM bit (REG0x12[1]) to 1.

0b: Disable this function. IIN_DPM is not disabled when CELL_BATPRESZ goes LOW. <default at POR>

1b: Enable this function. IIN_DPM is disabled when CELL_BATPRESZ goes LOW.
11 OTG_ON_CHRGOK R/W 0b

Add OTG to CHRG_OK

Drive CHRG_OK to HIGH when the device is in OTG mode.

0b: Disable <default at POR>

1b: Enable
10 EN_OOA R/W 1b

Out-of-Audio Enable

In both forward mode and OTG mode, switching frequency reduces with diminishing load, under extreme light load condition the switching frequency could be lower than 25kHz which is already in audible frequency range. By configuring EN_OOA=1b, the minimum PFM burst frequency is clamped at around 25kHz to avoid any audible noise.

0b: No limit of PFM burst frequency

1b: Set minimum PFM burst frequency to above 25 kHz to avoid audio noise <default at POR>
9 PWM_FREQ R/W 1b

Switching Frequency Selection: Recommend 1200kHz with 1uH, 800 kHz with 2.2 µH.

0b: 1200kHz

1b: 800kHz<default at POR>
8 DIS_STRGRV R/W 1b

Switching HS MOSFET turn on gate drive strength.

0b: Enable HS MOSFET strong turn on gate drive strength

1b: Disable HS MOSFET strong turn on gate drive strength <default at POR>
Table 9-11 ChargeOption0 Register (SMBus address = 12h) Field Descriptions
SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
7 EN_CMP_LATCH R/W

0b

The EN_CMP_LATCH bit, will latch the independent comparator output after it is triggered at low state. If enabled in PROCHOT profile REG34H[6]=1 , STAT_COMP bit REG0x21[6] keep 1b after triggered until read by host and clear

0b: Independent comparator output will not latch when it is low<default at POR>

1b: Independent comparator output will latch when it is low, host can clear CMPOUT pin by toggling this REG0x12[7] bit.
6 VSYS_UVP_ENZ R/W 0b

To disable system under voltage protection.

0b: VSYS under voltage protection is enabled <default at POR>

1b: VSYS under voltage protection is disabled
5 EN_LEARN R/W 0b

LEARN mode allows the battery to discharge and converter to shut off while the adapter is present . It calibrates the battery gas gauge over a complete discharge/charge cycle. When the host determines the battery voltage is below battery depletion threshold, the host switch the system back to adapter input by writing this bit back to 0b.

0b: Disable LEARN Mode <default at POR>

1b: Enable LEARN Mode
4 IADPT_GAIN R/W 0b

IADPT Amplifier Ratio

The ratio of voltage on IADPT and voltage across ACP and ACN.

0b: 20× <default at POR>

1b: 40×
3 IBAT_GAIN R/W 1b

IBAT Amplifier Ratio

The ratio of voltage on IBAT and voltage across SRP and SRN

0b: 8×

1b: 16× <default at POR>
2 EN_LDO R/W 1b

LDO Mode Enable

When battery voltage is below minimum system voltage (REG0x3E()), the charger is in pre-charge with LDO mode enabled.

0b: Disable LDO mode, BATFET fully ON. Precharge current is set by battery pack internal resistor. The system is regulated by the MaxChargeVoltage register.

1b: Enable LDO mode, Precharge current is set by the ChargeCurrent register and clamped below 384 mA (2 cell – 4 cell, 1cell VBAT<3.0V) or 2A (1cell 3.0V<VBAT<3.6V). The system is regulated by the VSYS_MIN register. <default at POR>
1 EN_IIN_DPM R/W 1b

IIN_DPM Enable

Host writes this bit to enable IIN_DPM regulation loop. When the IIN_DPM is disabled by the charger (refer to IIN_DPM_AUTO_DISABLE), this bit goes LOW.

0b: IIN_DPM disabled

1b: IIN_DPM enabled <default at POR>
0 CHRG_INHIBIT R/W 0b

Charge Inhibit

When this bit is 0, battery charging will start with valid values in the ChargeVoltage() register and the ChargeCurrent register.

0b: Enable Charge <default at POR>

1b: Inhibit Charge