Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case RMS ripple current is half of the charging current (plus system current there is any system load) when duty cycle is 0.5 in buck mode. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS current occurs where the duty cycle is closest to 50% and can be estimated by Equation 4:

Equation 4.

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be placed in front of R_AC current sensing and as close as possible to the power stage half bridge MOSFETs. Capacitance after R_AC before power stage half bridge should be limited to 10 nF + 1 nF referring to Figure 10-2 diagram. Because too large capacitance after R_AC could filter out R_AC current sensing ripple information. Voltage rating of the capacitor must be higher than normal input voltage level, 25-V rating or higher capacitor is preferred for 19-V to 20-V input voltage. The minimum input effective capacitance recommendation based on refers to Table 10-1.

Ceramic capacitors (MLCC) show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the input capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high input voltages and small capacitor packages. See the manufacturer's data sheet about the derating performance with a dc bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required effective capacitance value at the operating point. Considering the 25 V 0603 package MLCC capacitance derating under 19-V to 20-V input voltage, the recommended practical capacitors configuration can also be found in Table 10-1. Tantalum capacitors (POSCAP) can avoid dc-bias effect and temperature variation effect which is recommended for 90 W to 130 W higher power application.