SLUSDY3 December   2023 BQ25750

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics (BQ25750)
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Power-On-Reset
      2. 8.3.2 Device Power-Up From Battery Without Input Source
      3. 8.3.3 Device Power Up from Input Source
        1. 8.3.3.1 VAC Operating Window Programming (ACUV and ACOV)
        2. 8.3.3.2 REGN Regulator (REGN LDO)
        3. 8.3.3.3 Compensation-Free Buck-Boost Converter Operation
          1. 8.3.3.3.1 Light-Load Operation
        4. 8.3.3.4 Switching Frequency and Synchronization (FSW_SYNC)
        5. 8.3.3.5 Device HIZ Mode
      4. 8.3.4 Battery Charging Management
        1. 8.3.4.1 Autonomous Charging Cycle
          1. 8.3.4.1.1 Charge Current Programming (ICHG pin and ICHG_REG)
        2. 8.3.4.2 Li-Ion Battery Charging Profile
        3. 8.3.4.3 LiFePO4 Battery Charging Profile
        4. 8.3.4.4 Charging Termination for Li-ion and LiFePO4
        5. 8.3.4.5 Charging Safety Timer
        6. 8.3.4.6 Thermistor Qualification
          1. 8.3.4.6.1 JEITA Guideline Compliance in Charge Mode
          2. 8.3.4.6.2 Cold/Hot Temperature Window in Reverse Mode
      5. 8.3.5 Power Path Management
        1. 8.3.5.1 Dynamic Power Management: Input Voltage and Input Current Regulation
          1. 8.3.5.1.1 Input Current Regulation
            1. 8.3.5.1.1.1 ILIM_HIZ Pin
          2. 8.3.5.1.2 Input Voltage Regulation
            1. 8.3.5.1.2.1 Max Power Point Tracking (MPPT) for Solar PV Panel
      6. 8.3.6 Reverse Mode Power Direction
        1. 8.3.6.1 Auto Reverse Mode
      7. 8.3.7 Integrated 16-Bit ADC for Monitoring
      8. 8.3.8 Status Outputs (PG, STAT1, STAT2, and INT)
        1. 8.3.8.1 Power Good Indicator (PG)
        2. 8.3.8.2 Charging Status Indicator (STAT1, STAT2 Pins)
        3. 8.3.8.3 Interrupt to Host (INT)
      9. 8.3.9 Serial Interface
        1. 8.3.9.1 Data Validity
        2. 8.3.9.2 START and STOP Conditions
        3. 8.3.9.3 Byte Format
        4. 8.3.9.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.9.5 Target Address and Data Direction Bit
        6. 8.3.9.6 Single Write and Read
        7. 8.3.9.7 Multi-Write and Multi-Read
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
      2. 8.4.2 Register Bit Reset
    5. 8.5 BQ25750 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  ACUV / ACOV Input Voltage Operating Window Programming
          2. 9.2.1.2.2  Charge Voltage Selection
          3. 9.2.1.2.3  Switching Frequency Selection
          4. 9.2.1.2.4  Inductor Selection
          5. 9.2.1.2.5  Input (VAC / SYS) Capacitor
          6. 9.2.1.2.6  Output (VBAT) Capacitor
          7. 9.2.1.2.7  Sense Resistor (RAC_SNS and RBAT_SNS) and Current Programming
          8. 9.2.1.2.8  Power MOSFETs Selection
          9. 9.2.1.2.9  ACFETs and BATFETs Selection
          10. 9.2.1.2.10 Converter Fast Transient Response
        3. 9.2.1.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.4.1 Autonomous Charging Cycle

When battery charging is enabled (EN_CHG bit =1 and CE pin is LOW), the device autonomously completes a charging cycle without host involvement. The device charging parameters can be set by hardware through the FB pin to set regulation voltage and the ICHG pin to set charging current. The host can always control the charging operation and optimize the charging parameters by writing to the corresponding registers through I2C.

Table 8-3 Li-Ion & LiFePO4 Charging Parameter Default Settings
PARAMETER VALUE
Charge Stages Precharge → Fast Charge (CC) → Taper Charge (CV) → Termination → Recharge
FB Voltage Regulation Target (VFB_REG) 1.536 V
Battery Low Voltage (VBAT_LOWV ) 66.7% x VFB_REG = 1.0245 V
Recharge Voltage (VRECHG) 97.6% x VFB_REG =1.4991 V
Charging Current HW Limit (ICHG pin) ICHG = KICHG / RICHG
Pre-Charge Current HW Limit (ICHG pin) 20% x ICHG
Termination Current HW Limit (ICHG pin) 10% x ICHG
CV Timer Disabled
NTC Temperature Profile JEITA
Safety Timer 12 hours

A new charge cycle starts when the following conditions are valid:

  • VAC is within the ACUV and ACOV operating window
  • Device is not in HIZ mode (EN_HIZ = 0 and ILIM_HIZ pin voltage is below VIH_ILIM_HIZ)
  • REGN is above VREGN_OK
  • Battery charging is enabled (EN_CHG = 1 and CE pin is LOW )
  • No thermistor fault on TS
  • No safety timer fault

For lithium-ion battery charging, the charger device automatically terminates the charging cycle when the charging current is below termination threshold, charge voltage is above recharge threshold, and device is not in DPM mode. When a full battery voltage is discharged below recharge threshold (threshold selectable via VRECHG[1:0] bits), the device automatically starts a new charging cycle. After the charge is done, toggle either CE pin or EN_CHG bit can initiate a new charging cycle. In addition, the device offers a dedicated CV timer to stop the charging after a programmable period (CV_TMR bits) in CV mode, regardless of the charge current value.

The status register (CHARGE_STAT) indicates the different charging phases as:

  • 000 – Not Charging
  • 001 – Trickle Charge (VFB < VBAT_SHORT)
  • 010 – Pre-charge (VBAT_SHORT < VFB < VBAT_LOWV)
  • 011 – Fast-charge (CC mode)
  • 100 – Taper Charge (CV mode)
  • 101 – Reserved
  • 110 – Top-off Timer Active Charging
  • 111 – Charge Termination Done

When the charger transitions to any of these states, including when charge cycle is completed, an INT pulse is asserted to notify the host.

Supercapacitors do not require Trickle Charge or Pre-charge regions when their voltage is low. For supercapacitor charging, setting the EN_PRECHG bit to 0 can disable both of these charging regions. In this case, the charger outputs ICHG current as long as the feedback voltage (VFB) is below VFB_REG. The following settings are recommended for supercapacitor charging:

  • EN_PRECHG = 0
  • EN_TERM = 0
  • EN_CHG_TMR = 0