SLUSDY3 December   2023 BQ25750

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics (BQ25750)
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Power-On-Reset
      2. 8.3.2 Device Power-Up From Battery Without Input Source
      3. 8.3.3 Device Power Up from Input Source
        1. 8.3.3.1 VAC Operating Window Programming (ACUV and ACOV)
        2. 8.3.3.2 REGN Regulator (REGN LDO)
        3. 8.3.3.3 Compensation-Free Buck-Boost Converter Operation
          1. 8.3.3.3.1 Light-Load Operation
        4. 8.3.3.4 Switching Frequency and Synchronization (FSW_SYNC)
        5. 8.3.3.5 Device HIZ Mode
      4. 8.3.4 Battery Charging Management
        1. 8.3.4.1 Autonomous Charging Cycle
          1. 8.3.4.1.1 Charge Current Programming (ICHG pin and ICHG_REG)
        2. 8.3.4.2 Li-Ion Battery Charging Profile
        3. 8.3.4.3 LiFePO4 Battery Charging Profile
        4. 8.3.4.4 Charging Termination for Li-ion and LiFePO4
        5. 8.3.4.5 Charging Safety Timer
        6. 8.3.4.6 Thermistor Qualification
          1. 8.3.4.6.1 JEITA Guideline Compliance in Charge Mode
          2. 8.3.4.6.2 Cold/Hot Temperature Window in Reverse Mode
      5. 8.3.5 Power Path Management
        1. 8.3.5.1 Dynamic Power Management: Input Voltage and Input Current Regulation
          1. 8.3.5.1.1 Input Current Regulation
            1. 8.3.5.1.1.1 ILIM_HIZ Pin
          2. 8.3.5.1.2 Input Voltage Regulation
            1. 8.3.5.1.2.1 Max Power Point Tracking (MPPT) for Solar PV Panel
      6. 8.3.6 Reverse Mode Power Direction
        1. 8.3.6.1 Auto Reverse Mode
      7. 8.3.7 Integrated 16-Bit ADC for Monitoring
      8. 8.3.8 Status Outputs (PG, STAT1, STAT2, and INT)
        1. 8.3.8.1 Power Good Indicator (PG)
        2. 8.3.8.2 Charging Status Indicator (STAT1, STAT2 Pins)
        3. 8.3.8.3 Interrupt to Host (INT)
      9. 8.3.9 Serial Interface
        1. 8.3.9.1 Data Validity
        2. 8.3.9.2 START and STOP Conditions
        3. 8.3.9.3 Byte Format
        4. 8.3.9.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.9.5 Target Address and Data Direction Bit
        6. 8.3.9.6 Single Write and Read
        7. 8.3.9.7 Multi-Write and Multi-Read
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
      2. 8.4.2 Register Bit Reset
    5. 8.5 BQ25750 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  ACUV / ACOV Input Voltage Operating Window Programming
          2. 9.2.1.2.2  Charge Voltage Selection
          3. 9.2.1.2.3  Switching Frequency Selection
          4. 9.2.1.2.4  Inductor Selection
          5. 9.2.1.2.5  Input (VAC / SYS) Capacitor
          6. 9.2.1.2.6  Output (VBAT) Capacitor
          7. 9.2.1.2.7  Sense Resistor (RAC_SNS and RBAT_SNS) and Current Programming
          8. 9.2.1.2.8  Power MOSFETs Selection
          9. 9.2.1.2.9  ACFETs and BATFETs Selection
          10. 9.2.1.2.10 Converter Fast Transient Response
        3. 9.2.1.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.2.1.2.8 Power MOSFETs Selection

Four external N-channel MOSFETs are used for a synchronous switching buck-boost battery charger. The gate drivers are integrated into the IC with 5 V of gate drive voltage. An external gate drive voltage can be provided directly into the DRV_SUP pin for increased efficiency.

Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction loss and switching loss. For the top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance, RDS(ON), and the gate-to-drain charge, QGD. For the bottom side MOSFET, FOM is defined as the product of the MOSFET's on-resistance, RDS(ON), and the total gate charge, QG.

Equation 18. FOMtop = RDS(on) · QGD; FOMbottom = RDS(on) · QG

The lower the FOM value, the lower the total power loss. Usually lower RDS(ON) has higher cost with the same package size.

The top-side MOSFET loss includes conduction loss and switching loss. Taking buck mode operation as an example the power loss is a function of duty cycle (D=VOUT/VIN), charging current (ICHG), MOSFET's on-resistance (RDS(ON)_top), input voltage (VIN), switching frequency (fS), turn-on time (ton) and turn-off time (toff):

Equation 19. Ptop =Pcon_top+Psw_top
Equation 20. Pcon_top =D · IL_RMS2 · RDS(on)_top;
Equation 21. IL_RMS2=IL_DC2+Iripple2/12
  • IL_DC is the average inductor DC current;
  • Iripple is the inductor current ripple peak-to-peak value;
Equation 22. Psw_top =PIV_top+PQoss_top+PGate_top;

The first item Pcon_top represents the conduction loss which is straight forward. The second term Psw_top represents the multiple switching loss items in top MOSFET including voltage and current overlap losses (PIV_top), MOSFET parasitic output capacitance loss (PQoss_top) and gate drive loss (PGate_top). To calculate voltage and current overlap losses (PIV_top):

Equation 23. PIV_top =0.5x VIN · Ivalley · ton· fS+0.5x VIN · Ipeak · toff · fS
Equation 24. Ivalley =IL_DC- 0.5 · Iripple (inductor current valley value);
Equation 25. Ipeak =IL_DC+ 0.5 · Iripple (inductor current peak value);
  • ton is the MOSFET turn-on time that VDS falling time from VIN to almost zero (MOSFET turn on conduction voltage);
  • toff is the MOSFET turn-off time that IDS falling time from Ipeak to zero;

The MOSFET turn-on and turn-off times are given by:

Equation 26. GUID-66D54DC8-331A-4159-84C7-3FAB15FEA334-low.gif

where Qsw is the switching charge, Ion is the turn-on gate driving current, and Ioff is the turn-off gate driving current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge (QGD) and gate-to-source charge (QGS):

Equation 27. Qsw =QGD+QGS

Gate driving current can be estimated by REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total turn-on gate resistance (Ron), and turn-off gate resistance (Roff) of the gate driver:

Equation 28. GUID-2A574F33-73D8-4CE8-BFE8-F907B6945821-low.gif

To calculate top MOSFET parasitic output capacitance loss (PQoss_top):

Equation 29. PQoss_top =0.5 · VIN· Qoss · fS
  • Qoss is the MOSFET parasitic output charge which can be found in MOSFET datasheet. It is recommended to limit the total switch node capacitance CSW (nF) < 160/VIN; for example, for a 60-V application, it is recommended to keep the total CSW < 2.67 nF

To calculate top MOSFET gate drive loss (PGate_top):

Equation 30. PGate_top =VIN· QGate_top · fS
  • QGate_top is the top MOSFET gate charge which can be found in MOSFET datasheet;
  • Note here VIN is used instead of real gate drive voltage because the gate drive is generated based on LDO from VIN, the total gate drive related loss are all considered when VIN is used for gate drive loss calculation.
  • Alternatively, gate drive voltage can be supplied directly by external high efficiency supply into the DRV_SUP pin. In this case, the power loss to drive the gates becomes: PGate_top =VDRV_SUP· QGate_top · fS

The bottom-side MOSFET loss also includes conduction loss and switching loss:

Equation 31. Pbottom =Pcon_bottom+Psw_bottom
Equation 32. Pcon_bottom =(1 - D) · IL_RMS2 · RDS(on)_bottom;
Equation 33. Psw_bottom =PRR_bottom+PDead_bottom+PGate_bottom;

The first item Pcon_bottom represents the conduction loss which is straight forward. The second term Psw_bottom represents the multiple switching loss items in bottom MOSFET including reverse recovery losses (PRR_bottom), Dead time body diode conduction loss (PDead_bottom) and gate drive loss (PGate_bottom). The detail calculation can be found below:

Equation 34. PRR_bottom=VIN · Qrr · fS
  • Qrr is the bottom MOSFET reverse recovery charge which can be found in MOSFET data sheet;
Equation 35. PDead_bottom=VF · Ivalley · fS · tdead_rise+VF · Ipeak · fS · tdead_fall
  • VF is the body diode forward conduction voltage drop;
  • tdead_rise is the SW rising edge deadtime between top and bottom MOSFETs which is around 45 ns;
  • tdead_fall is the SW falling edge deadtime between top and bottom MOSFETs which is around 45 ns;

PGate_bottom can follow the same method as top MOSFET gate drive loss calculation approach.

Power-path FETs for providing power to SYS from either VAC or VBAT are selected as N-channel MOSFETs. The gate drivers are integrated into the IC with 10 V of gate drive voltage; however, the gate drive voltage can be reduced to 7 V using the PWRPATH_REDUCE_VDRV register bit if desired.