SLUSDY3 December   2023 BQ25750

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics (BQ25750)
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Power-On-Reset
      2. 8.3.2 Device Power-Up From Battery Without Input Source
      3. 8.3.3 Device Power Up from Input Source
        1. 8.3.3.1 VAC Operating Window Programming (ACUV and ACOV)
        2. 8.3.3.2 REGN Regulator (REGN LDO)
        3. 8.3.3.3 Compensation-Free Buck-Boost Converter Operation
          1. 8.3.3.3.1 Light-Load Operation
        4. 8.3.3.4 Switching Frequency and Synchronization (FSW_SYNC)
        5. 8.3.3.5 Device HIZ Mode
      4. 8.3.4 Battery Charging Management
        1. 8.3.4.1 Autonomous Charging Cycle
          1. 8.3.4.1.1 Charge Current Programming (ICHG pin and ICHG_REG)
        2. 8.3.4.2 Li-Ion Battery Charging Profile
        3. 8.3.4.3 LiFePO4 Battery Charging Profile
        4. 8.3.4.4 Charging Termination for Li-ion and LiFePO4
        5. 8.3.4.5 Charging Safety Timer
        6. 8.3.4.6 Thermistor Qualification
          1. 8.3.4.6.1 JEITA Guideline Compliance in Charge Mode
          2. 8.3.4.6.2 Cold/Hot Temperature Window in Reverse Mode
      5. 8.3.5 Power Path Management
        1. 8.3.5.1 Dynamic Power Management: Input Voltage and Input Current Regulation
          1. 8.3.5.1.1 Input Current Regulation
            1. 8.3.5.1.1.1 ILIM_HIZ Pin
          2. 8.3.5.1.2 Input Voltage Regulation
            1. 8.3.5.1.2.1 Max Power Point Tracking (MPPT) for Solar PV Panel
      6. 8.3.6 Reverse Mode Power Direction
        1. 8.3.6.1 Auto Reverse Mode
      7. 8.3.7 Integrated 16-Bit ADC for Monitoring
      8. 8.3.8 Status Outputs (PG, STAT1, STAT2, and INT)
        1. 8.3.8.1 Power Good Indicator (PG)
        2. 8.3.8.2 Charging Status Indicator (STAT1, STAT2 Pins)
        3. 8.3.8.3 Interrupt to Host (INT)
      9. 8.3.9 Serial Interface
        1. 8.3.9.1 Data Validity
        2. 8.3.9.2 START and STOP Conditions
        3. 8.3.9.3 Byte Format
        4. 8.3.9.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.9.5 Target Address and Data Direction Bit
        6. 8.3.9.6 Single Write and Read
        7. 8.3.9.7 Multi-Write and Multi-Read
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
      2. 8.4.2 Register Bit Reset
    5. 8.5 BQ25750 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  ACUV / ACOV Input Voltage Operating Window Programming
          2. 9.2.1.2.2  Charge Voltage Selection
          3. 9.2.1.2.3  Switching Frequency Selection
          4. 9.2.1.2.4  Inductor Selection
          5. 9.2.1.2.5  Input (VAC / SYS) Capacitor
          6. 9.2.1.2.6  Output (VBAT) Capacitor
          7. 9.2.1.2.7  Sense Resistor (RAC_SNS and RBAT_SNS) and Current Programming
          8. 9.2.1.2.8  Power MOSFETs Selection
          9. 9.2.1.2.9  ACFETs and BATFETs Selection
          10. 9.2.1.2.10 Converter Fast Transient Response
        3. 9.2.1.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-20231106-SS0I-F6LF-3S47-4MBTDM8PBK7N-low.svg Figure 6-1 BQ25750, RRV Package36-Pin VQFNTop View
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
SCL 1 I I2C Interface Clock – Connect SCL to the logic rail through a 10-kΩ resistor.
SDA 2 IO I2C Interface Data – Connect SDA to the logic rail through a 10-kΩ resistor.
INT 3 O Open Drain Interrupt Output – Connect the INT pin to a logic rail via 10-kΩ resistor. The INT pin sends an active low, 256-μs pulse to host to report the charger device status and faults.
STAT1 4 O Open Drain Charge Status 1 Output – STAT1 and STAT2 indicate various charger operations, see Table 8-6. Connect to the pull up rail via 10-kΩ resistor. The STAT1, STAT2 pin functions can be disabled when DIS_STAT_PINS bit is set to 1. When disabled, this pin can be used as a general purpose indicator via the FORCE_STAT1_ON bit.
STAT2 5 O Open Drain Charge Status 2 Output – STAT1 and STAT2 indicate various charger operations, see Table 8-6. Connect to the pull up rail via 10-kΩ resistor. The STAT1, STAT2 pin functions can be disabled when DIS_STAT_PINS bit is set to 1. When disabled, this pin can be used as a general purpose indicator via the FORCE_STAT2_ON bit.
PG 6 O Open Drain Active Low Power Good Indicator – Connect to the pull up rail via 10-kΩ resistor. LOW indicates a good input source if VAC is within the programmed ACUV / ACOV operating window. The PG pin function can be disabled when DIS_PG_PIN bit is set to 1. When disabled, this pin can be used as a general purpose indicator via the FORCE_STAT3_ON bit.
CE 7 IO Active Low Charge Enable Pin – Battery charging is enabled when EN_CHG bit is 1 and CE pin is LOW. CE pin must be pulled HIGH or LOW, do not leave floating. The CE pin function can be disabled when DIS_CE_PIN bit is set to 1. When disabled, this pin can be used as a general purpose indicator via the FORCE_STAT4_ON bit.
TS 8 I Temperature Qualification Voltage Input – Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to PGND. Charge suspends when TS pin voltage is out of range. Recommend 103AT-2 10-kΩ thermistor.
ICHG 9 I Charge Current Limit Setting – ICHG pin sets the maximum charge current, and can be used to monitor the charge current. A programming resistor to PGND is used to set the charge current limit as ICHG = KICHG / RICHG. When the device is under charge current regulation, the voltage at ICHG pin is VREF_ICHG. When ICHG pin voltage is less than VREF_ICHG, the actual charge current can be calculated as: IBAT = KICHG x VICHG / ( RICHG x VREF_ICHG). The actual charge current limit is the lower of the limits set by ICHG pin or the ICHG_REG register bits. This pin function can be disabled when EN_ICHG_PIN bit is 0. If ICHG pin is not used, this pin should be pulled to PGND, do not leave floating.
ILIM_HIZ 10 I Input Current Limit Setting and HIZ Mode Control Pin – ILIM_HIZ pin sets the maximum input current limit, can be used to monitor the input current and can be pulled HIGH to force device into HIZ mode. A programming resistor to PGND is used to set the input current limit as ILIM = KILIM / RILIM. When the device is under input current regulation, the voltage at ILIM_HIZ pin is VREF_ILIM. When ILIM_HIZ pin voltage is less than VREF_ILIM, the actual input current can be calculated as: IAC = KILIM x VILIM / ( RILIM x VREF_ILIM). The actual input current limit is the lower of the limits set by ILIM_HIZ pin or the IAC_DPM register bits. This pin function can be disabled when EN_ILIM_HIZ_PIN bit is 0. If ILIM_HIZ pin is not used, this pin should be pulled to PGND, do not leave floating.
FBG 11 I Voltage Feedback Divider Return – Connect to the bottom of battery feedback resistor. When charging, this pin is driven to PGND internally. When input voltage is outside of the ACUV / ACOV operating window, this pin is high-impedance, minimizing battery leakage current.
FB 12 I Charge Voltage Analog Feedback Adjustment – Connect the output of a resistive voltage divider from the battery terminals to this node to adjust the output battery regulation voltage.
SRN 13 I Charge Current-Sense Resistor, Negative Input – A 0.47-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the SRN pin to PGND for common-mode filtering.
SRP 14 I Charge Current-Sense Resistor, Positive Input – A 0.47-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from the SRP pin to PGND for common-mode filtering.
BATDRV 15 O N-Channel Battery FET Gate Drive – Connect directly to the BATFET gate. Pin drives the gate with 10 V relative to BATSRC to turn on BATFET when the input voltage is outside of the ACUV / ACOV operating window. An optional capacitor from BATDRV to BATSRC can be used to slow down the turn on transition.
BATSRC 16 I N-Channel Battery FET Source – Connect directly to the BATFETs common source.
PGND 17 I Tie this pin directly to PGND.
SW2 18 P Boost Side Half Bridge Switching Node – Connect to the source of boost HS FET and the drain of boost LS FET. Connect the inductor between SW1 and SW2.
HIDRV2 19 O Boost Side High-Side Gate Driver – Connect to the boost high-side N-channel MOSFET gate.
BTST2 20 P Boost Side High-Side Power MOSFET Gate Driver Power Supply – Connect a capacitor between BTST2 and SW2 to provide bias to the high-side MOSFET gate driver.
LODRV2 21 O Boost Side Low-Side Gate Driver – Connect to the boost low-side N-channel MOSFET gate.
PGND 22 P Power Ground Return – The high current ground connection for the low-side gate drivers.
DRV_SUP 23 P Charger Gate Drive Supply Input – Voltage on this pin is used to drive the gates of buck-boost converter switching FET. Connect a 4.7-μF ceramic capacitor from DRV_SUP to power ground. REGN LDO voltage can be used as the gate driver supply for all switching FETs by connecting REGN to DRV_SUP pin. In high-voltage applications, it is possible to directly provide the DRV_SUP voltage with an external supply up to 12 V to achieve higher switching efficiency. See Section 8.3.3.2 for more details.
REGN 24 P Charger Internal Linear Regulator Output – Connect a 4.7-μF ceramic capacitor from REGN to power ground. REGN LDO voltage can be used as the gate driver supply for all switching FETs by connecting REGN to DRV_SUP pin. In high-voltage applications, it is possible to directly provide the DRV_SUP voltage with an external supply up to 12 V to achieve higher switching efficiency. See Section 8.3.3.2 for more details.
LODRV1 25 O Buck Side Low-Side Gate Driver – Connect to the buck low-side N-channel MOSFET gate.
BTST1 26 P Buck Side High-Side Power MOSFET Gate Driver Power Supply – Connect a capacitor between BTST1 and SW1 to provide bias to the high-side MOSFET gate driver.
HIDRV1 27 O Buck Side High-Side Gate Driver – Connect to the buck high-side N-channel MOSFET gate.
SW1 28 P Buck Side Half Bridge Switching Node – Connect to the source of buck HS FET and the drain of buck LS FET. Connect the inductor between SW1 and SW2.
ACN 29 I Adapter Current-Sense Resistor, Negative Input – A 0.47-μF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the ACN pin to PGND for common-mode filtering.
ACP 30 I Adapter Current-Sense Resistor, Positive Input – A 0.47-μF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from the ACP pin to PGND for common-mode filtering
ACDRV 31 O N-Channel Input FET Gate Drive – Connect directly to the back-to-back input FETs (ACFETs) gates. Pin drives the gate with 10V to turn on ACFETs when the input voltage is inside of the ACUV / ACOV operating window. If input voltage is outside the valid operating window, this pin pulls to PGND to turn off the FETs. Connect a 15-V Zener diode from ACDRV to the common source of the ACFETs.
SYS 32 I System voltage sense point – Sense point for system voltage. If VAC is outside of the ACUV / ACOV operating window, the BATFET will only turn on once the SYS voltage falls below battery voltage (ideal-diode turn on). When Reverse Mode is enabled, this pin voltage is regulated to VSYS_REV.
VAC 33 P Input Voltage Detection and Power – VAC is the input bias to power the IC. Connect a 1-µF capacitor from pin to PGND.
ACUV 34 I Input Undervoltage Comparator – Connect a resistor divider from VAC to PGND to program the undervoltage protection. When this pin falls below VREF_ACUV, the device stops charging, disables the ACFETs and enables the BATFET. The hardware limit for input voltage regulation reference is VACUV_DPM. The actual input voltage regulation is the higher of the pin-programmed value and the VAC_DPM register value. If ACUV programming is not used, pull this pin to VAC, do not leave floating.
ACOV 35 I Input Overvoltage Comparator – Connect a resistor divider from VAC to PGND to program the overvoltage protection. When this pin rises above VREF_ACOV, the device stops charging, disables the ACFETs and enables the BATFET. If ACOV programming is not used, pull this pin to PGND, do not leave floating.
FSW_SYNC 36 I Switching Frequency and Synchronization Input – An external resistor is connected to the FSW_SYNC pin and PGND to set the nominal switching frequency. This pin can also be used to synchronize the PWM controller to an external clock with 200-kHz to 600-kHz frequency.
Thermal Pad 37 - Exposed pad beneath the IC – Always solder the thermal pad to the board, and have vias on the thermal pad plane star-connecting to PGND and ground plane for high-current power converter. It also serves as a thermal pad to dissipate the heat.