SLUSFO4 August   2024 BQ25758A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Power-On-Reset
      2. 7.3.2 Device Power-Up From Battery Without Input Source
      3. 7.3.3 Device Power Up from Input Source
        1. 7.3.3.1 VAC Operating Window Programming (ACUV and ACOV)
        2. 7.3.3.2 MODE Pin Configuration
        3. 7.3.3.3 REGN Regulator (REGN LDO)
        4. 7.3.3.4 Switching Frequency and Synchronization (FSW_SYNC)
        5. 7.3.3.5 Device HIZ Mode
      4. 7.3.4 Power Management
        1. 7.3.4.1 Output Voltage Programming (VOUT_REG)
        2. 7.3.4.2 Output Current Programming (IOUT pin and IOUT_REG)
        3. 7.3.4.3 Dynamic Power Management: Input Voltage and Input Current Regulation
          1. 7.3.4.3.1 Input Current Regulation
            1. 7.3.4.3.1.1 IIN Pin
            2. 7.3.4.3.1.2 Multi-Level Current Limit (Overload Mode)
          2. 7.3.4.3.2 Input Voltage Regulation
        4. 7.3.4.4 Bypass Mode
      5. 7.3.5 Bidirectional Power Flow and Programmability
      6. 7.3.6 Integrated 16-Bit ADC for Monitoring
      7. 7.3.7 Status Outputs (PG, STAT and INT)
        1. 7.3.7.1 Power Good Indicator (PG)
        2. 7.3.7.2 Interrupt to Host (INT)
      8. 7.3.8 Protections
        1. 7.3.8.1 Voltage and Current Monitoring
          1. 7.3.8.1.1 VAC Over-voltage Protection (VAC_OVP)
          2. 7.3.8.1.2 VAC Under-voltage Protection (VAC_UVP)
          3. 7.3.8.1.3 Reverse Mode Over-voltage Protection (REV_OVP)
          4. 7.3.8.1.4 Reverse Mode Under-voltage Protection (REV_UVP)
          5. 7.3.8.1.5 DRV_SUP Under-voltage and Over-voltage Protection (DRV_OKZ)
          6. 7.3.8.1.6 REGN Under-voltage Protection (REGN_OKZ)
        2. 7.3.8.2 Thermal Shutdown (TSHUT)
      9. 7.3.9 Serial Interface
        1. 7.3.9.1 Data Validity
        2. 7.3.9.2 START and STOP Conditions
        3. 7.3.9.3 Byte Format
        4. 7.3.9.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 7.3.9.5 Target Address and Data Direction Bit
        6. 7.3.9.6 Single Write and Read
        7. 7.3.9.7 Multi-Write and Multi-Read
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host Mode and Default Mode
      2. 7.4.2 Register Bit Reset
    5. 7.5 BQ25758A Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application (Buck-Boost configuration)
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 ACUV / ACOV Input Voltage Operating Window Programming
          2. 8.2.1.2.2 Switching Frequency Selection
          3. 8.2.1.2.3 Inductor Selection
          4. 8.2.1.2.4 Input (VAC) Capacitor
          5. 8.2.1.2.5 Output (VBAT) Capacitor
          6. 8.2.1.2.6 Sense Resistor (RAC_SNS and RBAT_SNS) and Current Programming
          7. 8.2.1.2.7 Converter Fast Transient Response
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application (Buck-only configuration)
        1. 8.2.2.1 Design Requirements
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tape and Reel Information
    3. 13.3 Mechanical Data

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RRV|36
Thermal pad, mechanical data (Package|Pins)

7.5 BQ25758A Registers

Table 7-3 lists the memory-mapped registers for the BQ25758A registers. All register offset addresses not listed in Table 7-3 should be considered as reserved locations and the register contents should not be modified.

Table 7-3 BQ25758A Registers
Address Acronym Register Name Section
0x2 REG0x02_Output_Current_Limit Output Current Limit Go
0x4 REG0x04_Output_Voltage_Limit Output Voltage Limit Go
0x6 REG0x06_Input_Current_DPM_Limit Input Current DPM Limit Go
0x8 REG0x08_Input_Voltage_DPM_Limit Input Voltage DPM Limit Go
0xA REG0x0A_Reverse_Mode_Input_Current_Limit Reverse Mode Input Current Limit Go
0xC REG0x0C_Reverse_Mode_Input_Voltage_Limit Reverse Mode Input Voltage Limit Go
0x15 REG0x15_Timer_Control Timer Control Go
0x17 REG0x17_Converter_Control Converter Control Go
0x18 REG0x18_Pin_Control Pin Control Go
0x19 REG0x19_Power_Path_and_Reverse_Mode_Control Power Path and Reverse Mode Control Go
0x1B REG0x1B_TS_Threshold_Control TS Threshold Control Go
0x1C REG0x1C_TS_Region_Behavior_Control TS Region Behavior Control Go
0x1D REG0x1D_TS_Reverse_Mode_Threshold_Control TS Reverse Mode Threshold Control Go
0x1E REG0x1E_Bypass_and_Overload_Control Bypass and Overload Control Go
0x21 REG0x21_Status_1 Status 1 Go
0x22 REG0x22_Status_2 Status 2 Go
0x23 REG0x23_Status_3 Status 3 Go
0x24 REG0x24_Fault_Status Fault Status Go
0x25 REG0x25_Flag_1 Flag 1 Go
0x26 REG0x26_Flag_2 Flag 2 Go
0x27 REG0x27_Fault_Flag Fault Flag Go
0x28 REG0x28_Mask_1 Mask 1 Go
0x29 REG0x29_Mask_2 Mask 2 Go
0x2A REG0x2A_Fault_Mask Fault Mask Go
0x2B REG0x2B_ADC_Control ADC Control Go
0x2C REG0x2C_ADC_Channel_Control ADC Channel Control Go
0x2D REG0x2D_IAC_ADC IAC ADC Go
0x2F REG0x2F_IOUT_ADC IOUT ADC Go
0x31 REG0x31_VAC_ADC VAC ADC Go
0x33 REG0x33_VOUT_ADC VOUT ADC Go
0x37 REG0x37_TS_ADC TS ADC Go
0x3B REG0x3B_Gate_Driver_Strength_Control Gate Driver Strength Control Go
0x3C REG0x3C_Gate_Driver_Dead_Time_Control Gate Driver Dead Time Control Go
0x3D REG0x3D_Part_Information Part Information Go
0x62 REG0x62_Reverse_Mode_Current Reverse Mode Current Go

Complex bit access types are encoded to fit into small table cells. Table 7-4 shows the codes that are used for access types in this section.

Table 7-4 BQ25758A Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.5.1 REG0x02_Output_Current_Limit Register (Address = 0x2) [Reset = 0x0640]

REG0x02_Output_Current_Limit is shown in Table 7-5.

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I2C REG0x03=[15:8], I2C REG0x02=[7:0]

Table 7-5 REG0x02_Output_Current_Limit Register Field Descriptions
BitFieldTypeResetNotesDescription
15:11RESERVEDR0x0 Reserved
10:2IOUT_REGR/W0x190Reset by:
REG_RESET
WATCHDOG		 Output Current Regulation Limit with 5mΩ ROUT_SNS:
Actual current is the lower of IOUT_REG and IOUT pin POR: 20000mA (190h)
Range: 400mA-20000mA (8h-190h)
Clamped Low
Clamped High
Bit Step: 50mA
1:0RESERVEDR0x0 Reserved

7.5.2 REG0x04_Output_Voltage_Limit Register (Address = 0x4) [Reset = 0x03E8]

REG0x04_Output_Voltage_Limit is shown in Table 7-6.

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I2C REG0x05=[15:8], I2C REG0x04=[7:0]

Table 7-6 REG0x04_Output_Voltage_Limit Register Field Descriptions
BitFieldTypeResetNotesDescription
15:14RESERVEDR0x0 Reserved
13:2VOUT_REGR/W0xFAReset by:
REG_RESET		 Output Voltage Regulation Limit: POR: 5000mV (FAh)
Range: 3300mV-60000mV (A5h-BB8h)
Clamped Low
Clamped High
Bit Step: 20mV
1:0RESERVEDR0x0 Reserved

7.5.3 REG0x06_Input_Current_DPM_Limit Register (Address = 0x6) [Reset = 0x0640]

REG0x06_Input_Current_DPM_Limit is shown in Table 7-7.

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I2C REG0x07=[15:8], I2C REG0x06=[7:0]

Table 7-7 REG0x06_Input_Current_DPM_Limit Register Field Descriptions
BitFieldTypeResetNotesDescription
15:11RESERVEDR0x0 Reserved
10:2IAC_DPMR/W0x190Reset by:
REG_RESET		 Input Current DPM Regulation Limit with 5mΩ RAC_SNS:
Actual input current limit is the lower of IAC_DPM and IIN pin POR: 20000mA (190h)
Range: 400mA-20000mA (8h-190h)
Clamped Low
Clamped High
Bit Step: 50mA
1:0RESERVEDR0x0 Reserved

7.5.4 REG0x08_Input_Voltage_DPM_Limit Register (Address = 0x8) [Reset = 0x0348]

REG0x08_Input_Voltage_DPM_Limit is shown in Table 7-8.

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I2C REG0x09=[15:8], I2C REG0x08=[7:0]

Table 7-8 REG0x08_Input_Voltage_DPM_Limit Register Field Descriptions
BitFieldTypeResetNotesDescription
15:14RESERVEDR0x0 Reserved
13:2VAC_DPMR/W0xD2Reset by:
REG_RESET		 Input Voltage Regulation Limit: POR: 4400mV (DCh)
Range: 4400mV-60000mV (DCh-BB8h)
Clamped Low
Clamped High
Bit Step: 20mV
1:0RESERVEDR0x0 Reserved

7.5.5 REG0x0A_Reverse_Mode_Input_Current_Limit Register (Address = 0xA) [Reset = 0x0640]

REG0x0A_Reverse_Mode_Input_Current_Limit is shown in Table 7-9.

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I2C REG0x0B=[15:8], I2C REG0x0A=[7:0]

Table 7-9 REG0x0A_Reverse_Mode_Input_Current_Limit Register Field Descriptions
BitFieldTypeResetNotesDescription
15:11RESERVEDR0x0 Reserved
10:2IAC_REVR/W0x190Reset by:
REG_RESET		 Input Current Regulation in Reverse Mode with 5mΩ RAC_SNS: POR: 20000mA (190h)
Range: 400mA-20000mA (8h-190h)
Clamped Low
Clamped High
Bit Step: 50mA
1:0RESERVEDR0x0 Reserved

7.5.6 REG0x0C_Reverse_Mode_Input_Voltage_Limit Register (Address = 0xC) [Reset = 0x03E8]

REG0x0C_Reverse_Mode_Input_Voltage_Limit is shown in Table 7-10.

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I2C REG0x0D=[15:8], I2C REG0x0C=[7:0]

Table 7-10 REG0x0C_Reverse_Mode_Input_Voltage_Limit Register Field Descriptions
BitFieldTypeResetNotesDescription
15:14RESERVEDR0x0 Reserved
13:2VAC_REVR/W0xFAReset by:
REG_RESET		 VAC Voltage Regulation in Reverse Mode: POR: 5000mV (FAh)
Range: 3300mV-60000mV (A5h-BB8h)
Clamped Low
Clamped High
Bit Step: 20mV
1:0RESERVEDR0x0 Reserved

7.5.7 REG0x15_Timer_Control Register (Address = 0x15) [Reset = 0x10]

REG0x15_Timer_Control is shown in Table 7-11.

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Table 7-11 REG0x15_Timer_Control Register Field Descriptions
BitFieldTypeResetNotesDescription
7:6RESERVEDR0x0 Reserved
5:4WATCHDOGR/W0x1Reset by:
REG_RESET		 Watchdog timer control: 00b = Disable
01b = 40s
10b = 80s
11b = 160s
3RESERVEDR0x0 Reserved
2:1RESERVEDR0x0 Reserved
0RESERVEDR0x0 Reserved

7.5.8 REG0x17_Converter_Control Register (Address = 0x17) [Reset = 0x09]

REG0x17_Converter_Control is shown in Table 7-12.

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Table 7-12 REG0x17_Converter_Control Register Field Descriptions
BitFieldTypeResetNotesDescription
7:6RESERVEDR0x0 Reserved
5WD_RSTR/W0x0Reset by:
REG_RESET		 I2C Watchdog timer reset control: 0b = Normal
1b = Reset (bit goes back to 0 after timer reset)
4DIS_CE_PINR/W0x0Reset by:
REG_RESET		 /CE pin function disable: 0b = /CE pin enabled
1b = /CE pin disabled
3EN_CHG_BIT_RESET_BEHAVIORR/W0x1Reset by:
REG_RESET		 Controls the EN_CHG bit behavior when WATCHDOG expires: 0b = EN_CHG bit resets to 0
1b = EN_CHG bit resets to 1
2EN_HIZR/W0x0Reset by:
REG_RESET
WATCHDOG
Adapter Plug In		 HIZ mode enable: 0b = Disable
1b = Enable
1EN_IBAT_LOADR/W0x0Sinks current from SRP to GND. Recommend to disable IBAT ADC (IBAT_ADC_DIS = 1) while this bit is active.
Reset by:
REG_RESET
WATCHDOG		 Battery Load (IBAT_LOAD) Enable: 0b = Disabled
1b = Enabled
0EN_CHGR/W0x1Reset by:
REG_RESET
WATCHDOG		 Enable control: 0b = Disable
1b = Enable

7.5.9 REG0x18_Pin_Control Register (Address = 0x18) [Reset = 0xC0]

REG0x18_Pin_Control is shown in Table 7-13.

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Table 7-13 REG0x18_Pin_Control Register Field Descriptions
BitFieldTypeResetNotesDescription
7EN_IOUT_PINR/W0x1Reset by:
REG_RESET
WATCHDOG		 IOUT pin function enable: 0b = IOUT pin disabled
1b = IOUT pin enabled
6EN_IIN_PINR/W0x1Reset by:
REG_RESET
WATCHDOG		 IIN pin function enable: 0b = IIN pin disabled
1b = IIN pin enabled
5DIS_PG_PINR/W0x0Reset by:
REG_RESET		 PG pin function disable: 0b = PG pin enabled
1b = PG pin disabled
4DIS_STAT_PINR/W0x0Reset by:
REG_RESET		 STAT pin function disable: 0b = STAT pin enabled
1b = STAT pin disabled
3FORCE_STAT4_ONR/W0x0Reset by:
REG_RESET		 CE_STAT4 pin override:
Can only be forced on if DIS_CE_PIN = 1 0b = CE_STAT4 open-drain off
1b = CE_STAT4 pulls LOW
2FORCE_STAT3_ONR/W0x0Reset by:
REG_RESET		 PG_STAT3 pin override:
Can only be forced on if DIS_PG_PIN = 1 0b = PG_STAT3 open-drain off
1b = PG_STAT3 pulls LOW
1RESERVEDR0x0 Reserved
0FORCE_STAT_ONR/W0x0Reset by:
REG_RESET		 STAT pin override:
Can only be forced on if DIS_STAT_PIN = 1 0b = STAT open-drain off
1b = STAT pulls LOW

7.5.10 REG0x19_Power_Path_and_Reverse_Mode_Control Register (Address = 0x19) [Reset = 0x00]

REG0x19_Power_Path_and_Reverse_Mode_Control is shown in Table 7-14.

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Table 7-14 REG0x19_Power_Path_and_Reverse_Mode_Control Register Field Descriptions
BitFieldTypeResetNotesDescription
7REG_RSTR/W0x0Reset by:
REG_RESET		 Register reset to default values: 0b = Not reset
1b = Reset (bit goes back to 0 after register reset)
6EN_IAC_LOADR/W0x0Reset by:
REG_RESET
WATCHDOG		 VAC Load (IAC_LOAD) Enable: 0b = Disabled
1b = Enabled
5EN_PFMR/W0x0This bit is reset upon a valid SYNC signal detection on FSW_SYNC pin. Host can set this bit back to 1 to force PFM operation even with a valid SYNC input
Reset by:
REG_RESET		 Enable PFM mode to improve light-load efficiency: 0b = Disable (Fixed-frequency DCM operation)
1b = Enable (PFM operation)
4RESERVEDR0x0 Reserved
3PWRPATH_REDUCE_VDRVR/W0x0Reset by:
REG_RESET
WATCHDOG		 Bypass Mode Gate-Drive Voltage Select: 0b = 10V
1b = 7V
2RESERVEDR0x0 Reserved
1RESERVEDR0x0
0EN_REVR/W0x0Reset by:
REG_RESET
WATCHDOG
Adapter Plug In		 Reverse Mode control: 0b = Disable
1b = Enable

7.5.11 REG0x1B_TS_Threshold_Control Register (Address = 0x1B) [Reset = 0x82]

REG0x1B_TS_Threshold_Control is shown in Table 7-15.

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Table 7-15 REG0x1B_TS_Threshold_Control Register Field Descriptions
BitFieldTypeResetNotesDescription
7:6TS_T5R/W0x2 Reserved
5:4RESERVEDR0x0 Reserved
3:2RESERVEDR0x0 Reserved
1:0RESERVEDR/W0x2 Reserved

7.5.12 REG0x1C_TS_Region_Behavior_Control Register (Address = 0x1C) [Reset = 0x00]

REG0x1C_TS_Region_Behavior_Control is shown in Table 7-16.

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Table 7-16 REG0x1C_TS_Region_Behavior_Control Register Field Descriptions
BitFieldTypeResetNotesDescription
7RESERVEDR0x0 Reserved
6:5RESERVEDR0x0 Reserved
4RESERVEDR0x0 Reserved
3:2RESERVEDR0x0 Reserved
1RESERVEDR0x0EN_VREG_TEMP_COMP and EN_JEITA cannot be set to 1 at the same time. Reserved
0RESERVEDR/W0x0Reset by:
REG_RESET		 Reserved

7.5.13 REG0x1D_TS_Reverse_Mode_Threshold_Control Register (Address = 0x1D) [Reset = 0x40]

REG0x1D_TS_Reverse_Mode_Threshold_Control is shown in Table 7-17.

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Table 7-17 REG0x1D_TS_Reverse_Mode_Threshold_Control Register Field Descriptions
BitFieldTypeResetNotesDescription
7:6BHOTR/W0x1Reset by:
REG_RESET		 Reverse Mode TS HOT temperature threshold control: 00b = 37.7% (55C)
01b = 34.2% (60C)
10b = 31.25%(65C)
11b = Disable
5BCOLDR/W0x0Reset by:
REG_RESET		 Reverse Mode TS COLD temperature threshold control: 0b = 77.15% (-10C)
1b = 80% (-20C)
4:0RESERVEDR0x0 Reserved

7.5.14 REG0x1E_Bypass_and_Overload_Control Register (Address = 0x1E) [Reset = 0x20]

REG0x1E_Bypass_and_Overload_Control is shown in Table 7-18.

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Table 7-18 REG0x1E_Bypass_and_Overload_Control Register Field Descriptions
BitFieldTypeResetNotesDescription
7RESERVEDR0x0 Reserved
6TOVLD_SETR/W0x0Reset by:
REG_RESET		 TOVLD timer control: 0b = 25ms
1b = 50ms
5SYSREV_UVR/W0x1Reset by:
REG_RESET		 Reverse Mode System UVP: 0b = 80% of VSYS_REV target
1b = Fixed at 3.3V
4EN_BYPASSR/W0x0Bypass mode only supported in forward mode, not operational in reverse mode.
Reset by:
REG_RESET
WATCHDOG		 Bypass mode control:
Note the device automatically clears this bit and sets EN_HIZ bit when the output current exceeds IOUT_REG register value in bypass mode. 0b = Disable
1b = Enable
3EN_OVLD_TMAXR/W0x0Reset by:
REG_RESET		 TMAX counter control: 0b = Disable TMAX: allows new overload event after tOVLD and current falling below ILIM1
1b = Enable TMAX: allow new overload event after tMAX, even if current does not fall below ILIM1
2EN_OVLD_3LR/W0x0Reset by:
REG_RESET		 Three-level overload mode control: 0b = Disable
1b = Enable
1OVLD_ILIM2R/W0x0Reset by:
REG_RESET		 Overload higher current limit (percentage above IIN or IOUT): 0b = 1.5
1b = 2
0EN_OVLDR/W0x0Reset by:
REG_RESET		 Overload Mode control: 0b = Disable
1b = Enable

7.5.15 REG0x21_Status_1 Register (Address = 0x21) [Reset = 0x00]

REG0x21_Status_1 is shown in Table 7-19.

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Table 7-19 REG0x21_Status_1 Register Field Descriptions
BitFieldTypeResetNotesDescription
7ADC_DONE_STATR0x0 ADC conversion status (in one-shot mode only): 0b = Conversion not complete
1b = Conversion complete
6IAC_DPM_STATR0x0 Input Current regulation status: 0b = Normal
1b = In Input Current regulation (ILIM pin or IAC_DPM)
5VAC_DPM_STATR0x0 Input Voltage regulation status: 0b = Normal
1b = In Input Voltage regulation (VAC_DPM or VSYS_REV)
4RESERVEDR0x0 Reserved
3WD_STATR0x0 I2C Watchdog timer status: 0b = Normal
1b = WD timer expired
2:0CHARGE_STATR0x0 Converter status: 000b = Not switching
001b = Reserved
010b = Reserved
011b = CC Mode
100b = CV Mode
101b = CV Mode
110b = CV Mode
111b = Reserved

7.5.16 REG0x22_Status_2 Register (Address = 0x22) [Reset = 0x00]

REG0x22_Status_2 is shown in Table 7-20.

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Table 7-20 REG0x22_Status_2 Register Field Descriptions
BitFieldTypeResetNotesDescription
7PG_STATR0x0 Input Power Good status: 0b = Not Power Good
1b = Power Good
6:4TS_STATR0x0 TS status: 000b = Normal
001b = TS Warm
010b = TS Cool
011b = TS Cold
100b = TS Hot
3:2RESERVEDR0x0 Reserved
1:0RESERVEDR0x0 Reserved

7.5.17 REG0x23_Status_3 Register (Address = 0x23) [Reset = 0x00]

REG0x23_Status_3 is shown in Table 7-21.

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Table 7-21 REG0x23_Status_3 Register Field Descriptions
BitFieldTypeResetNotesDescription
7:6RESERVEDR0x0 Reserved
5:4FSW_SYNC_STATR0x0 FSW_SYNC pin status: 00b = Normal, no external clock detected
01b = Valid ext. clock detected
10b = Pin fault (frequency out-of-range)
11b = Reserved
3RESERVEDR0x0 Reserved
2REVERSE_STATR0x0 Converter Reverse Mode status: 0b = Reverse Mode off
1b = Reverse Mode On
1RESERVEDR0x0 Reserved
0RESERVEDR0x0 Reserved

7.5.18 REG0x24_Fault_Status Register (Address = 0x24) [Reset = 0x00]

REG0x24_Fault_Status is shown in Table 7-22.

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Table 7-22 REG0x24_Fault_Status Register Field Descriptions
BitFieldTypeResetNotesDescription
7VAC_UV_STATR0x0 Input under-voltage status: 0b = Input Normal
1b = Device in Input under-voltage protection
6VAC_OV_STATR0x0 Input over-voltage status: 0b = Input Normal
1b = Device in Input over-voltage protection
5IBAT_OCP_STATR0x0 Battery over-current status: 0b = Battery current normal
1b = Battery over-current detected
4VBAT_OV_STATR0x0 Battery over-voltage status: 0b = Normal
1b = Device in Battery over-voltage protection
3TSHUT_STATR0x0 Thermal shutdown status: 0b = Normal
1b = Device in thermal shutdown protection
2RESERVEDR0x0 Reserved
1DRV_OKZ_STATR0x0In battery-only mode with ADC disabled, this bit always reads '1' DRV_SUP pin voltage status: 0b = Normal
1b = DRV_SUP pin voltage is out of valid range
0RESERVEDR0x0 Reserved

7.5.19 REG0x25_Flag_1 Register (Address = 0x25) [Reset = 0x00]

REG0x25_Flag_1 is shown in Table 7-23.

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Table 7-23 REG0x25_Flag_1 Register Field Descriptions
BitFieldTypeResetNotesDescription
7ADC_DONE_FLAGR0x0 ADC conversion INT flag (in one-shot mode only):
Note: always reads 0 in continuous mode Access: R (ClearOnRead)
0b = Conversion not complete
1b = Conversion complete
6IAC_DPM_FLAGR0x0 Input Current regulation INT flag: Access: R (ClearOnRead)
0b = Normal
1b = Device entered Input Current regulation
5VAC_DPM_FLAGR0x0 Input Voltage regulation INT flag: Access: R (ClearOnRead)
0b = Normal
1b = Device entered Input Voltage regulation
4RESERVEDR0x0 Reserved
3WD_FLAGR0x0 I2C Watchdog timer INT flag: Access: R (ClearOnRead)
0b = Normal
1b = WD_STAT rising edge detected
2RESERVEDR0x0 Reserved
1RESERVEDR0x0 Reserved
0CHARGE_FLAGR0x0 Charge cycle INT flag: Access: R (ClearOnRead)
0b = Not charging
1b = CHARGE_STAT[2:0] bits changed (transition to any state)

7.5.20 REG0x26_Flag_2 Register (Address = 0x26) [Reset = 0x00]

REG0x26_Flag_2 is shown in Table 7-24.

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Table 7-24 REG0x26_Flag_2 Register Field Descriptions
BitFieldTypeResetNotesDescription
7PG_FLAGR0x0 Input Power Good INT flag: Access: R (ClearOnRead)
0b = Normal
1b = PG signal toggle detected
6RESERVEDR0x0 Reserved
5RESERVEDR0x0 Reserved
4TS_FLAGR0x0 TS INT flag: Access: R (ClearOnRead)
0b = Normal
1b = TS_STAT[2:0] bits changed (transitioned to any state)
3REVERSE_FLAGR0x0 Reverse Mode INT flag: Access: R (ClearOnRead)
0b = Normal
1b = Reverse Mode toggle detected
2RESERVEDR0x0 Reserved
1FSW_SYNC_FLAGR0x0 FSW_SYNC pin signal INT flag: Access: R (ClearOnRead)
0b = Normal
1b = FSW_SYNC status changed
0RESERVEDR0x0 Reserved

7.5.21 REG0x27_Fault_Flag Register (Address = 0x27) [Reset = 0x00]

REG0x27_Fault_Flag is shown in Table 7-25.

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Table 7-25 REG0x27_Fault_Flag Register Field Descriptions
BitFieldTypeResetNotesDescription
7VAC_UV_FLAGR0x0 Input under-voltage INT flag: Access: R (ClearOnRead)
0b = Normal
1b = Entered input under-voltage fault
6VAC_OV_FLAGR0x0 Input over-voltage INT flag: Access: R (ClearOnRead)
0b = Normal
1b = Entered Input over-voltage fault
5IBAT_OCP_FLAGR0x0 Battery over-current INT flag: Access: R (ClearOnRead)
0b = Normal
1b = Entered Battery over-current fault
4VBAT_OV_FLAGR0x0 Battery over-voltage INT flag: Access: R (ClearOnRead)
0b = Normal
1b = Entered battery over-voltage fault
3TSHUT_FLAGR0x0 Thermal shutdown INT flag: Access: R (ClearOnRead)
0b = Normal
1b = Entered TSHUT fault
2RESERVEDR0x0 Reserved
1DRV_OKZ_FLAGR0x0 DRV_SUP pin voltage INT flag: Access: R (ClearOnRead)
0b = Normal
1b = DRV_SUP pin fault detected
0RESERVEDR0x0 Reserved

7.5.22 REG0x28_Mask_1 Register (Address = 0x28) [Reset = 0x00]

REG0x28_Mask_1 is shown in Table 7-26.

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Table 7-26 REG0x28_Mask_1 Register Field Descriptions
BitFieldTypeResetNotesDescription
7ADC_DONE_MASKR/W0x0Reset by:
REG_RESET		 ADC conversion INT mask (in one-shot mode only): 0b = ADC_DONE produces INT pulse
1b = ADC_DONE does not produce INT pulse
6IAC_DPM_MASKR/W0x0Reset by:
REG_RESET		 Input Current regulation INT mask: 0b = IAC_DPM_FLAG produces INT pulse
1b = IAC_DPM_FLAG does not produce INT pulse
5VAC_DPM_MASKR/W0x0Reset by:
REG_RESET		 Input Voltage regulation INT mask: 0b = VAC_DPM_FLAG produces INT pulse
1b = VAC_DPM_FLAG does not produce INT pulse
4RESERVEDR0x0 Reserved
3WD_MASKR/W0x0Reset by:
REG_RESET		 I2C Watchdog timer INT mask: 0b = WD expiration produces INT pulse
1b = WD expiration does not produce INT pulse
2RESERVEDR0x0 Reserved
1RESERVEDR0x0 Reserved
0CHARGE_MASKR/W0x0Reset by:
REG_RESET		 Charge cycle INT mask: 0b = CHARGE_STAT change produces INT pulse
1b = CHARGE_STAT change does not produces INT pulse

7.5.23 REG0x29_Mask_2 Register (Address = 0x29) [Reset = 0x00]

REG0x29_Mask_2 is shown in Table 7-27.

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Table 7-27 REG0x29_Mask_2 Register Field Descriptions
BitFieldTypeResetNotesDescription
7PG_MASKR/W0x0Reset by:
REG_RESET		 Input Power Good INT mask: 0b = PG toggle produces INT pulse
1b = PG toggle does not produce INT pulse
6RESERVEDR0x0 Reserved
5RESERVEDR0x0 Reserved
4TS_MASKR/W0x0Reset by:
REG_RESET		 TS INT mask: 0b = TS_STAT change produces INT pulse
1b = TS_STAT change does not produce INT pulse
3REVERSE_MASKR/W0x0Reset by:
REG_RESET		 Reverse Mode INT mask: 0b = REVERSE_STAT toggle produces INT pulse
1b = REVERSE_STAT toggle does no produce INT pulse
2RESERVEDR0x0 Reserved
1FSW_SYNC_MASKR/W0x0Reset by:
REG_RESET		 FSW_SYNC pin signal INT mask: 0b = FSW_SYNC status change produces INT pulse
1b = FSW_SYNC status change does not produce INT pulse
0RESERVEDR0x0 Reserved

7.5.24 REG0x2A_Fault_Mask Register (Address = 0x2A) [Reset = 0x00]

REG0x2A_Fault_Mask is shown in Table 7-28.

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Table 7-28 REG0x2A_Fault_Mask Register Field Descriptions
BitFieldTypeResetNotesDescription
7VAC_UV_MASKR/W0x0Reset by:
REG_RESET		 Input under-voltage INT mask: 0b = Input under-voltage event produces INT pulse
1b = Input under-voltage event does not produce INT pulse
6VAC_OV_MASKR/W0x0Reset by:
REG_RESET		 Input over-voltage INT mask: 0b = Input over-voltage event produces INT pulse
1b = Input over-voltage event does not produce INT pulse
5IBAT_OCP_MASKR/W0x0Reset by:
REG_RESET		 Battery over-current INT mask: 0b = Battery over-current event produces INT pulse
1b = Battery over-current event does not produce INT pulse
4VBAT_OV_MASKR/W0x0Reset by:
REG_RESET		 Battery over-voltage INT mask: 0b = Battery over-voltage event produces INT pulse
1b = Battery over-voltage event does not produce INT pulse
3TSHUT_MASKR/W0x0Reset by:
REG_RESET		 Thermal shutdown INT mask: 0b = TSHUT event produces INT pulse
1b = TSHUT event does not produce INT pulse
2RESERVEDR0x0 Reserved
1DRV_OKZ_MASKR/W0x0Reset by:
REG_RESET		 DRV_SUP pin voltage INT mask: 0b = DRV_SUP pin fault produces INT pulse
1b = DRV_SUP pin fault does not produce INT pulse
0RESERVEDR0x0 Reserved

7.5.25 REG0x2B_ADC_Control Register (Address = 0x2B) [Reset = 0x60]

REG0x2B_ADC_Control is shown in Table 7-29.

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Table 7-29 REG0x2B_ADC_Control Register Field Descriptions
BitFieldTypeResetNotesDescription
7ADC_ENR/W0x0When EN_VREG_TEMP_COMP = 1, the ADC will be automatically enabled, regardless of the status of ADC_EN
Reset by:
REG_RESET
WATCHDOG		 ADC control: 0b = Disable ADC
1b = Enable ADC
6ADC_RATER/W0x1Reset by:
REG_RESET		 ADC conversion rate control: 0b = Continuous conversion
1b = One-shot conversion
5:4ADC_SAMPLER/W0x2Reset by:
REG_RESET		 ADC sample speed: 00b = 15 bit effective resolution
01b = 14 bit effective resolution
10b = 13 bit effective resolution
11b = Reserved
3ADC_AVGR/W0x0Reset by:
REG_RESET		 ADC average control: 0b = Single value
1b = Running average
2ADC_AVG_INITR/W0x0Reset by:
REG_RESET		 ADC average initial value control: 0b = Start average using existing register value
1b = Start average using new ADC conversion
1:0RESERVEDR0x0 Reserved

7.5.26 REG0x2C_ADC_Channel_Control Register (Address = 0x2C) [Reset = 0x0A]

REG0x2C_ADC_Channel_Control is shown in Table 7-30.

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Table 7-30 REG0x2C_ADC_Channel_Control Register Field Descriptions
BitFieldTypeResetNotesDescription
7IAC_ADC_DISR/W0x0Reset by:
REG_RESET		 IAC ADC control 0b = Enable
1b = Disable
6IOUT_ADC_DISR/W0x0Recommend to disable IOUT ADC channel when EN_IBAT_LOAD bit is 1
Reset by:
REG_RESET		 IOUT ADC control 0b = Enable
1b = Disable
5VAC_ADC_DISR/W0x0Reset by:
REG_RESET		 VAC ADC control 0b = Enable
1b = Disable
4VOUT_ADC_DISR/W0x0Reset by:
REG_RESET		 VOUT ADC control 0b = Enable
1b = Disable
3RESERVEDR0x0 Reserved
2TS_ADC_DISR/W0x0Reset by:
REG_RESET		 TS ADC control 0b = Enable
1b = Disable
1RESERVEDR0x0 Reserved
0RESERVEDR0x0 Reserved

7.5.27 REG0x2D_IAC_ADC Register (Address = 0x2D) [Reset = 0x0000]

REG0x2D_IAC_ADC is shown in Table 7-31.

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I2C REG0x2E=[15:8], I2C REG0x2D=[7:0]

Table 7-31 REG0x2D_IAC_ADC Register Field Descriptions
BitFieldTypeResetNotesDescription
15:0IAC_ADCR0x0 IAC ADC reading with 5mΩ RAC_SNS:
Reported as 2s complement POR: 0mA(0h)
Format: 2s Complement
Range: -20000mA - 20000mA (9E58h-61A8h)
Clamped Low
Clamped High
Bit Step: 0.8mA

7.5.28 REG0x2F_IOUT_ADC Register (Address = 0x2F) [Reset = 0x0000]

REG0x2F_IOUT_ADC is shown in Table 7-32.

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I2C REG0x30=[15:8], I2C REG0x2F=[7:0]

Table 7-32 REG0x2F_IOUT_ADC Register Field Descriptions
BitFieldTypeResetNotesDescription
15:0IOUT_ADCR0x0 IOUT ADC reading with 5mΩ RBAT_SNS:
Reported as 2s complement POR: 0mA (0h)
Format: 2s Complement
Range: -20000mA-20000mA (D8F0h-2710h)
Clamped Low
Clamped High
Bit Step: 2mA

7.5.29 REG0x31_VAC_ADC Register (Address = 0x31) [Reset = 0x0000]

REG0x31_VAC_ADC is shown in Table 7-33.

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I2C REG0x32=[15:8], I2C REG0x31=[7:0]

Table 7-33 REG0x31_VAC_ADC Register Field Descriptions
BitFieldTypeResetNotesDescription
15:0VAC_ADCR0x0 VAC ADC reading:
Reported as unsigned integer POR: 0mV (0h)
Format: 2s Complement
Range: 0mV-65534mV (0h-7FFFh)
Clamped Low
Bit Step: 2mV

7.5.30 REG0x33_VOUT_ADC Register (Address = 0x33) [Reset = 0x0000]

REG0x33_VOUT_ADC is shown in Table 7-34.

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I2C REG0x34=[15:8], I2C REG0x33=[7:0]

Table 7-34 REG0x33_VOUT_ADC Register Field Descriptions
BitFieldTypeResetNotesDescription
15:0VOUT_ADCR0x0 VOUT ADC reading:
Reported as unsigned integer POR: 0mV (0h)
Format: 2s Complement
Range: 0mV-65534mV (0h-7FFFh)
Clamped Low
Bit Step: 2mV

7.5.31 REG0x37_TS_ADC Register (Address = 0x37) [Reset = 0x0000]

REG0x37_TS_ADC is shown in Table 7-35.

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I2C REG0x38=[15:8], I2C REG0x37=[7:0]

Table 7-35 REG0x37_TS_ADC Register Field Descriptions
BitFieldTypeResetNotesDescription
15:0TS_ADCR0x0 TS ADC reading as percentage of REGN:
Reported as unsigned integer POR: 0%(0h)
Range: 0% - 99.90234375% (0h-3FFh)
Clamped High
Bit Step: 0.09765625%

7.5.32 REG0x3B_Gate_Driver_Strength_Control Register (Address = 0x3B) [Reset = 0x00]

REG0x3B_Gate_Driver_Strength_Control is shown in Table 7-36.

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Table 7-36 REG0x3B_Gate_Driver_Strength_Control Register Field Descriptions
BitFieldTypeResetNotesDescription
7:6BOOST_HS_DRVR/W0x0Reset by:
REG_RESET		 Boost High Side FET Gate Driver Strength: 00b = Fastest
01b = Faster
10b = Slower
11b = Slowest
5:4BUCK_HS_DRVR/W0x0Reset by:
REG_RESET		 Buck High Side FET Gate Driver Strength: 00b = Fastest
01b = Faster
10b = Slower
11b = Slowest
3:2BOOST_LS_DRVR/W0x0Reset by:
REG_RESET		 Boost Low Side FET Gate Driver Strength: 00b = Fastest
01b = Faster
10b = Slower
11b = Slowest
1:0BUCK_LS_DRVR/W0x0Reset by:
REG_RESET		 Buck Low Side FET Gate Driver Strength: 00b = Fastest
01b = Faster
10b = Slower
11b = Slowest

7.5.33 REG0x3C_Gate_Driver_Dead_Time_Control Register (Address = 0x3C) [Reset = 0x00]

REG0x3C_Gate_Driver_Dead_Time_Control is shown in Table 7-37.

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Table 7-37 REG0x3C_Gate_Driver_Dead_Time_Control Register Field Descriptions
BitFieldTypeResetNotesDescription
7:4RESERVEDR0x0 Reserved
3:2BOOST_DEAD_TIMER/W0x0Reset by:
REG_RESET		 Boost Side FETs Dead Time Control: 00b = 45ns
01b = 75ns
10b = 105ns
11b = 135ns
1:0BUCK_DEAD_TIMER/W0x0Reset by:
REG_RESET		 Buck Side FETs Dead Time Control: 00b = 45ns
01b = 75ns
10b = 105ns
11b = 135ns

7.5.34 REG0x3D_Part_Information Register (Address = 0x3D) [Reset = 0x08]

REG0x3D_Part_Information is shown in Table 7-38.

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Table 7-38 REG0x3D_Part_Information Register Field Descriptions
BitFieldTypeResetNotesDescription
7:6RESERVEDR0x0 Reserved
5:3PART_NUMR0x1 Part Number:
001 - BQ25758A
2:0DEV_REVR0x0 Device Revision:

7.5.35 REG0x62_Reverse_Mode_Current Register (Address = 0x62) [Reset = 0x02]

REG0x62_Reverse_Mode_Current is shown in Table 7-39.

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Table 7-39 REG0x62_Reverse_Mode_Current Register Field Descriptions
BitFieldTypeResetNotesDescription
7:6IBAT_REVR/W0x0Reset by:
REG_RESET		 Reverse mode current limit: 00b = 20A
01b = 15A
10b = 10A
11b = 5A
5:2RESERVEDR0x0 Reserved
1EN_CONV_FAST_TRANSIENTR/W0x1Reset by:
REG_RESET		 Enable converter fast transient response - 0b = Disable
1b = Enable
0RESERVEDR0x0 Reserved