SLUSFO4 August   2024 BQ25758A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Power-On-Reset
      2. 7.3.2 Device Power-Up From Battery Without Input Source
      3. 7.3.3 Device Power Up from Input Source
        1. 7.3.3.1 VAC Operating Window Programming (ACUV and ACOV)
        2. 7.3.3.2 MODE Pin Configuration
        3. 7.3.3.3 REGN Regulator (REGN LDO)
        4. 7.3.3.4 Switching Frequency and Synchronization (FSW_SYNC)
        5. 7.3.3.5 Device HIZ Mode
      4. 7.3.4 Power Management
        1. 7.3.4.1 Output Voltage Programming (VOUT_REG)
        2. 7.3.4.2 Output Current Programming (IOUT pin and IOUT_REG)
        3. 7.3.4.3 Dynamic Power Management: Input Voltage and Input Current Regulation
          1. 7.3.4.3.1 Input Current Regulation
            1. 7.3.4.3.1.1 IIN Pin
            2. 7.3.4.3.1.2 Multi-Level Current Limit (Overload Mode)
          2. 7.3.4.3.2 Input Voltage Regulation
        4. 7.3.4.4 Bypass Mode
      5. 7.3.5 Bidirectional Power Flow and Programmability
      6. 7.3.6 Integrated 16-Bit ADC for Monitoring
      7. 7.3.7 Status Outputs (PG, STAT and INT)
        1. 7.3.7.1 Power Good Indicator (PG)
        2. 7.3.7.2 Interrupt to Host (INT)
      8. 7.3.8 Protections
        1. 7.3.8.1 Voltage and Current Monitoring
          1. 7.3.8.1.1 VAC Over-voltage Protection (VAC_OVP)
          2. 7.3.8.1.2 VAC Under-voltage Protection (VAC_UVP)
          3. 7.3.8.1.3 Reverse Mode Over-voltage Protection (REV_OVP)
          4. 7.3.8.1.4 Reverse Mode Under-voltage Protection (REV_UVP)
          5. 7.3.8.1.5 DRV_SUP Under-voltage and Over-voltage Protection (DRV_OKZ)
          6. 7.3.8.1.6 REGN Under-voltage Protection (REGN_OKZ)
        2. 7.3.8.2 Thermal Shutdown (TSHUT)
      9. 7.3.9 Serial Interface
        1. 7.3.9.1 Data Validity
        2. 7.3.9.2 START and STOP Conditions
        3. 7.3.9.3 Byte Format
        4. 7.3.9.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 7.3.9.5 Target Address and Data Direction Bit
        6. 7.3.9.6 Single Write and Read
        7. 7.3.9.7 Multi-Write and Multi-Read
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host Mode and Default Mode
      2. 7.4.2 Register Bit Reset
    5. 7.5 BQ25758A Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application (Buck-Boost configuration)
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 ACUV / ACOV Input Voltage Operating Window Programming
          2. 8.2.1.2.2 Switching Frequency Selection
          3. 8.2.1.2.3 Inductor Selection
          4. 8.2.1.2.4 Input (VAC) Capacitor
          5. 8.2.1.2.5 Output (VBAT) Capacitor
          6. 8.2.1.2.6 Sense Resistor (RAC_SNS and RBAT_SNS) and Current Programming
          7. 8.2.1.2.7 Converter Fast Transient Response
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application (Buck-only configuration)
        1. 8.2.2.1 Design Requirements
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tape and Reel Information
    3. 13.3 Mechanical Data

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RRV|36
Thermal pad, mechanical data (Package|Pins)

5 Pin Configuration and Functions

BQ25758A BQ25758A, RRV Package36-Pin VQFNTop View Figure 5-1 BQ25758A, RRV Package36-Pin VQFNTop View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
SCL 1 DI I2C Interface Clock – Connect SCL to the logic rail through a 10-kΩ resistor.
SDA 2 DIO I2C Interface Data – Connect SDA to the logic rail through a 10-kΩ resistor.
INT 3 DO Open Drain Interrupt Output – Connect the INT pin to a logic rail via 10-kΩ resistor. The INT pin sends an active low, 256-μs pulse to host to report the controller device status and faults.
STAT 4 DO Open Drain Status Output – Connect to the pull up rail via 10-kΩ resistor. The STAT pin function can be disabled when DIS_STAT_PIN bit is set to 1. When disabled, this pin can be used as a general purpose indicator via the FORCE_STAT_ON bit.
NC 5 - No Connect - Leave this pin floating, do not tie to PGND
PG/STAT3 6 DO Open Drain Active Low Power Good Indicator – Connect to the pull up rail via 10-kΩ resistor. LOW indicates a good input source if VAC is within the programmed ACUV / ACOV operating window. The PG pin function can be disabled when DIS_PG_PIN bit is set to 1. When disabled, this pin can be used as a general purpose indicator via the FORCE_STAT3_ON bit.
CE/STAT4 7 DIO Active Low Enable Pin – Power conversion is enabled when EN_CHG bit is 1 and CE pin is LOW. CE pin must be pulled HIGH or LOW, do not leave floating. The CE pin function can be disabled when DIS_CE_PIN bit is set to 1. When disabled, this pin can be used as a general purpose indicator via the FORCE_STAT4_ON bit.
TS / NC 8 AI Temperature Qualification Voltage Input – This pin's function is normally disabled. If not needed, leave this pin floating.
To enable pin functionality, set EN_TS register bit to 1. Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to PGND. Power conversion suspends when TS pin voltage is out of range. Recommend 103AT-2 10-kΩ thermistor.
IOUT 9 AI Output Current Limit Setting – IOUT pin sets the maximum output current, and can be used to monitor the output current. A programming resistor to PGND is used to set the output current limit as IIOUT = KIOUT / RIOUT. When the device is under output current regulation, the voltage at IOUT pin is VREF_IOUT. When IOUT pin voltage is less than VREF_IOUT, the actual output current can be calculated as: IOUT = KIOUT x VIOUT / ( RIOUT x VREF_IOUT). The actual output current limit is the lower of the limits set by IOUT pin or the IOUT_REG register bits. This pin function can be disabled when EN_IOUT_PIN bit is 0. If IOUT pin is not used, this pin should be pulled to PGND, do not leave floating.
IIN 10 AI Input Current Limit Setting – IIN pin sets the maximum input current, and can be used to monitor the input current. A programming resistor to PGND is used to set the input current limit as ILIM = KILIM / RIIN. When the device is under input current regulation, the voltage at IIN pin is VREF_IILIM. When IIN pin voltage is less than VREF_ILIM, the actual input current can be calculated as: IAC = KILIM x VIIN / ( RIIN x VREF_ILIM). The actual input current limit is the lower of the limits set by IIN pin or the IAC_DPM register bits. This pin function can be disabled when EN_IIN_PIN bit is 0. If IIN pin is not used, this pin should be pulled to PGND, do not leave floating.
NC 11 - No Connect - Leave this pin floating , do not tie to PGND
VO_SNS 12 AI Output Voltage Sensing – Kelvin connect directly to the output voltage regulation point.
SRN 13 AI Current-Sense Resistor, Negative Input – A 0.47-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the SRN pin to PGND for common-mode filtering.
SRP 14 AI Current-Sense Resistor, Positive Input – A 0.47-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from the SRP pin to PGND for common-mode filtering.
NC 15 - No Connect - Leave this pin floating, do not tie to PGND
NC 16 - No Connect - Leave this pin floating, do not tie to PGND
MODE 17 AI Mode Programming resistor – Connect a resistor from this pin to PGND to select between buck-boost or buck-only operation. Refer to MODE Pin Configuration section for more details.
SW2 18 AI Boost Side Half Bridge Switching Node –
HIDRV2 19 AO Boost Side High-Side Gate Driver – Connect to the boost high-side N-channel MOSFET gate.
BTST2 20 P Boost Side High-Side Power MOSFET Gate Driver Power Supply – Connect a capacitor between BTST2 and SW2 to provide bias to the high-side MOSFET gate driver.
LODRV2 21 AO Boost Side Low-Side Gate Driver – Connect to the boost low-side N-channel MOSFET gate.
PGND 22 - Power Ground Return – The high current ground connection for the low-side gate drivers.
DRV_SUP 23 P Gate Drive Supply Input – Voltage on this pin is used to drive the gates of buck-boost converter switching FET. Connect a 4.7-μF ceramic capacitor from DRV_SUP to power ground. REGN LDO voltage can be used as the gate driver supply for all switching FETs by connecting REGN to DRV_SUP pin. In high-voltage applications, it is possible to directly provide the DRV_SUP voltage with an external supply up to 12 V to achieve higher switching efficiency. See Section 7.3.3.3 for more details.
REGN 24 P Internal Linear Regulator Output – Connect a 4.7-μF ceramic capacitor from REGN to power ground. REGN LDO voltage can be used as the gate driver supply for all switching FETs by connecting REGN to DRV_SUP pin. In high-voltage applications, it is possible to directly provide the DRV_SUP voltage with an external supply up to 12 V to achieve higher switching efficiency. See Section 7.3.3.3 for more details.
LODRV1 25 AO Buck Side Low-Side Gate Driver – Connect to the buck low-side N-channel MOSFET gate.
BTST1 26 P Buck Side High-Side Power MOSFET Gate Driver Power Supply – Connect a capacitor between BTST1 and SW1 to provide bias to the high-side MOSFET gate driver.
HIDRV1 27 AO Buck Side High-Side Gate Driver – Connect to the buck high-side N-channel MOSFET gate.
SW1 28 AI Buck Side Half Bridge Switching Node –
ACN 29 AI Adapter Current-Sense Resistor, Negative Input A 0.47-μF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the ACN pin to PGND for common-mode filtering.
ACP 30 AI Adapter Current-Sense Resistor, Positive Input A 0.47-μF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from the ACP pin to PGND for common-mode filtering
NC 31 - No Connect - Leave this pin floating, do not tie to PGND
VAC 32 P Input Voltage Detection and Power VAC is the input bias to power the IC. Connect a 1µF capacitor from pin to PGND. When Reverse Mode is enabled, pin 32 is regulated to VAC_REV.
33
ACUV 34 AI VAC Undervoltage Comparator Input – Connect a resistor divider from VAC to PGND to program the undervoltage protection. When this pin falls below VREF_ACUV, the device stops operation. The hardware limit for input voltage regulation reference is VACUV_DPM. The actual input voltage regulation setting is the higher of the pin-programmed value and the VAC_DPM register value. If ACUV programming is not used, pull this pin to VAC, do not leave floating.
ACOV 35 AI VAC Overvoltage Comparator Input – Connect a resistor divider from VAC to PGND to program the overvoltage protection. When this pin rises above VREF_ACOV, the device stops operation. If ACOV programming is not used, pull this pin to PGND, do not leave floating.
FSW_SYNC 36 DAI Switching Frequency and Synchronization Input – An external resistor is connected to the FSW_SYNC pin and PGND to set the nominal switching frequency. This pin can also be used to synchronize the PWM controller to an external clock.
Thermal Pad 37 - Exposed pad beneath the IC – Always solder the thermal pad to the board, and have vias on the thermal pad plane star-connecting to PGND and ground plane for high-current power converter. It also serves as a thermal pad to dissipate the heat.