SLUSEK7 September   2024 BQ25773

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics BQ2577X
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequence
      2. 7.3.2  MODE Pin Detection
      3. 7.3.3  REGN Regulator (REGN LDO)
      4. 7.3.4  Independent Comparator Function
      5. 7.3.5  Battery Charging Management
        1. 7.3.5.1 Autonomous Charging Cycle
        2. 7.3.5.2 Battery Charging Profile
        3. 7.3.5.3 Charging Termination
        4. 7.3.5.4 Charging Safety Timer
      6. 7.3.6  Temperature Regulation (TREG)
      7. 7.3.7  Vmin Active Protection (VAP) When Battery Only Mode
      8. 7.3.8  Two Level Battery Discharge Current Limit
      9. 7.3.9  Fast Role Swap Feature
      10. 7.3.10 CHRG_OK Indicator
      11. 7.3.11 Input and Charge Current Sensing
      12. 7.3.12 Input Current and Voltage Limit Setup
      13. 7.3.13 Battery Cell Configuration
      14. 7.3.14 Device HIZ State
      15. 7.3.15 USB On-The-Go (OTG)
      16. 7.3.16 Quasi Dual Phase Converter Operation
      17. 7.3.17 Continuous Conduction Mode (CCM)
      18. 7.3.18 Pulse Frequency Modulation (PFM)
      19. 7.3.19 Switching Frequency and Dithering Feature
      20. 7.3.20 Current and Power Monitor
        1. 7.3.20.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 7.3.20.2 High-Accuracy Power Sense Amplifier (PSYS)
      21. 7.3.21 Input Source Dynamic Power Management
      22. 7.3.22 Integrated 16-Bit ADC for Monitoring
      23. 7.3.23 Input Current Optimizer (ICO)
      24. 7.3.24 Two-Level Adapter Current Limit (Peak Power Mode)
      25. 7.3.25 Processor Hot Indication
        1. 7.3.25.1 PROCHOT During Low Power Mode
        2. 7.3.25.2 PROCHOT Status
      26. 7.3.26 Device Protection
        1. 7.3.26.1  Watchdog Timer (WD)
        2. 7.3.26.2  Input Overvoltage Protection (ACOV)
        3. 7.3.26.3  Input Overcurrent Protection (ACOC)
        4. 7.3.26.4  System Overvoltage Protection (SYSOVP)
        5. 7.3.26.5  Battery Overvoltage Protection (BATOVP)
        6. 7.3.26.6  Battery Charge Overcurrent Protection (BATCOC)
        7. 7.3.26.7  Battery Discharge Overcurrent Protection (BATDOC)
        8. 7.3.26.8  BATFET Charge Current Clamp Protection under LDO Regulation Mode
        9. 7.3.26.9  Sleep Comparator Protection Between VBUS and ACP_A (SC_VBUSACP)
        10. 7.3.26.10 High Duty Buck Exit Comparator Protection (HDBCP)
        11. 7.3.26.11 REGN Power Good Protection (REGN_PG)
        12. 7.3.26.12 System Under Voltage Lockout (VSYS_UVP) and Hiccup Mode
        13. 7.3.26.13 OTG Mode Over Voltage Protection (OTG_OVP)
        14. 7.3.26.14 OTG Mode Under Voltage Protection (OTG_UVP)
        15. 7.3.26.15 Thermal Shutdown (TSHUT)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forward Mode
        1. 7.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 7.4.1.2 Battery Charging
      2. 7.4.2 USB On-The-Go Mode
      3. 7.4.3 Pass Through Mode (PTM)-Patented Technology
      4. 7.4.4 Learn Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
        1. 7.5.1.1 Timing Diagrams
        2. 7.5.1.2 Data Validity
        3. 7.5.1.3 START and STOP Conditions
        4. 7.5.1.4 Byte Format
        5. 7.5.1.5 Acknowledge (ACK) and Not Acknowledge (NACK)
        6. 7.5.1.6 Target Address and Data Direction Bit
        7. 7.5.1.7 Single Read and Write
        8. 7.5.1.8 Multi-Read and Multi-Write
        9. 7.5.1.9 Write 2-Byte I2C Commands
    6. 7.6 BQ25773 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Snubber and Filter for Voltage Spike Damping
        2. 8.2.2.2 ACP-ACN Input Filter
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Power MOSFETs Selection
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Layout Example Reference Top View
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • REE|36
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 REGN Regulator (REGN LDO)

The REGN LDO regulator provides a regulated bias supply for the IC and external pull up. Additionally, REGN voltage is also used to drive the buck-boost switching FETs. The pull-up rail of CELL_BATPRES pin and ILIM_HIZ pin can be connected to REGN as well. When there is no valid external 5V voltage source available on the system then REGN LDO will be powered from either the VBUS pin or VSYS pin. REGN power selector selects the lower of VBUS and VSYS if both greater than 6V; should select the higher of VBUS and VSYS is they're both lower than 6V; and should select the one higher than 6V if there is only one higher than 6V. Both REGN_A and REGN_B pins are connected to REGN LDO internally, no external connections between REGN_A and REGN_B are needed, however 2.2uF local decoupling capacitance are needed for both REGN_A and REGN_B pins.

When there is a qualified 5V supply in the system, it can be leveraged as a REGN source. This can reduce power loss from the internal LDO, especially when both VBUS and VSYS are much higher than 5V. The LDO can be configured to be over-driven by external 5V source. Then REGN pin will change from an analog output pin to an analog input pin. REGN_EXT bit is employed to configure in the following method.

  • When there is no qualified external 5V source, host should configure REGN_EXT=0b(default status), then the internal REGN LDO regulation output voltage is 5V to normally support internal bias and switching MOSFET gate drive. There is an internal current limit to prevent LDO from over load. The current limit level is IREGN_LIM_CHARGING and it is marked as current limit 1.
  • When there is dedicated qualified external 5V source(above 4.8V and below VREGN_OV_RISE) and REGN is the only load on external source, host should configure REGN_EXT=1b to reduce internal REGN LDO regulation output voltage to be VREGN_REG_EXT(4.5V), then external 5V regulator can over drive internal LDO. Maximum500mA current limit is needed for external power supply to prevent over current damaging on internal bootstrap diode. Application diagram is referring to Figure 7-1.
  • When the external 5V source (above 4.8V and below VREGN_OV_RISE) is also supporting other loads besides REGN, a dedicated blocking circuit is needed to prevent REGN current from sourcing into external loads before external 5V buck converter ramp up shown in Figure 7-2. Before external 5V regulator power good(PG) is active, the QBLK serves to block external loading impact on REGN_A pin. After external 5V ramps up, external 5V regulation PG is active and QBLK is turned on to distribute 5V to REGN_A pin. Host should configure REGN_EXT=1b to reduce internal REGN LDO regulation output voltage to be VREGN_REG_EXT(4.5V), then external 5V regulator can over drive to internal LDO automatically.
  • When external 5V source is above VREGN_OV_RISE, the charger should stop switching, pull down CHRG_OK pin and trigger FAULT_REGN status bit referring to Section 7.3.26.11.
BQ25773 External Dedicated 5-V Source Over Drive REGN Figure 7-1 External Dedicated 5-V Source Over Drive REGN
BQ25773 External 5-V Source with Load Over Drive REGN Figure 7-2 External 5-V Source with Load Over Drive REGN

The power dissipation for driving the gates via the REGN LDO is: PREGN = (VAC - VREGN) QG(TOT)*fSW, where QG(TOT) is the sum of the total gate charge for all practical switching FETs (1A,1B,2A,2B,3 and 4) and fSW is the programmed switching frequency.

Under battery only condition, it is flexible to configure REGN on and off through below method:

  • When charger is configured in low power mode(EN_LWPWR=1b), REGN by default is turned off(EN_REGN_LWPWR=0b). If customer needs REGN voltage to supply circuit, the charger enables REGN by setting EN_REGN_LWPWR=1b. In order to save quiescent current under low power mode, REGN current capability is scaled down to 5 mA typical and 3 mA minimum. When it receives host command to start up converter, like OTG or VAP mode is enabled, then REGN should automatically recover to full scale to support large gate drive current demand even with EN_LWPWR=1b.
  • When charger is configured in performance mode(EN_LWPWR=0b), REGN should be turned on with full scale capability neglecting EN_REGN_LWPWR configuration. This is needed to support OTG, VAP, PSYS, IBAT, PROCHOT, and ADC features.