SLUSEK7 September   2024 BQ25773

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics BQ2577X
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequence
      2. 7.3.2  MODE Pin Detection
      3. 7.3.3  REGN Regulator (REGN LDO)
      4. 7.3.4  Independent Comparator Function
      5. 7.3.5  Battery Charging Management
        1. 7.3.5.1 Autonomous Charging Cycle
        2. 7.3.5.2 Battery Charging Profile
        3. 7.3.5.3 Charging Termination
        4. 7.3.5.4 Charging Safety Timer
      6. 7.3.6  Temperature Regulation (TREG)
      7. 7.3.7  Vmin Active Protection (VAP) When Battery Only Mode
      8. 7.3.8  Two Level Battery Discharge Current Limit
      9. 7.3.9  Fast Role Swap Feature
      10. 7.3.10 CHRG_OK Indicator
      11. 7.3.11 Input and Charge Current Sensing
      12. 7.3.12 Input Current and Voltage Limit Setup
      13. 7.3.13 Battery Cell Configuration
      14. 7.3.14 Device HIZ State
      15. 7.3.15 USB On-The-Go (OTG)
      16. 7.3.16 Quasi Dual Phase Converter Operation
      17. 7.3.17 Continuous Conduction Mode (CCM)
      18. 7.3.18 Pulse Frequency Modulation (PFM)
      19. 7.3.19 Switching Frequency and Dithering Feature
      20. 7.3.20 Current and Power Monitor
        1. 7.3.20.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 7.3.20.2 High-Accuracy Power Sense Amplifier (PSYS)
      21. 7.3.21 Input Source Dynamic Power Management
      22. 7.3.22 Integrated 16-Bit ADC for Monitoring
      23. 7.3.23 Input Current Optimizer (ICO)
      24. 7.3.24 Two-Level Adapter Current Limit (Peak Power Mode)
      25. 7.3.25 Processor Hot Indication
        1. 7.3.25.1 PROCHOT During Low Power Mode
        2. 7.3.25.2 PROCHOT Status
      26. 7.3.26 Device Protection
        1. 7.3.26.1  Watchdog Timer (WD)
        2. 7.3.26.2  Input Overvoltage Protection (ACOV)
        3. 7.3.26.3  Input Overcurrent Protection (ACOC)
        4. 7.3.26.4  System Overvoltage Protection (SYSOVP)
        5. 7.3.26.5  Battery Overvoltage Protection (BATOVP)
        6. 7.3.26.6  Battery Charge Overcurrent Protection (BATCOC)
        7. 7.3.26.7  Battery Discharge Overcurrent Protection (BATDOC)
        8. 7.3.26.8  BATFET Charge Current Clamp Protection under LDO Regulation Mode
        9. 7.3.26.9  Sleep Comparator Protection Between VBUS and ACP_A (SC_VBUSACP)
        10. 7.3.26.10 High Duty Buck Exit Comparator Protection (HDBCP)
        11. 7.3.26.11 REGN Power Good Protection (REGN_PG)
        12. 7.3.26.12 System Under Voltage Lockout (VSYS_UVP) and Hiccup Mode
        13. 7.3.26.13 OTG Mode Over Voltage Protection (OTG_OVP)
        14. 7.3.26.14 OTG Mode Under Voltage Protection (OTG_UVP)
        15. 7.3.26.15 Thermal Shutdown (TSHUT)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forward Mode
        1. 7.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 7.4.1.2 Battery Charging
      2. 7.4.2 USB On-The-Go Mode
      3. 7.4.3 Pass Through Mode (PTM)-Patented Technology
      4. 7.4.4 Learn Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
        1. 7.5.1.1 Timing Diagrams
        2. 7.5.1.2 Data Validity
        3. 7.5.1.3 START and STOP Conditions
        4. 7.5.1.4 Byte Format
        5. 7.5.1.5 Acknowledge (ACK) and Not Acknowledge (NACK)
        6. 7.5.1.6 Target Address and Data Direction Bit
        7. 7.5.1.7 Single Read and Write
        8. 7.5.1.8 Multi-Read and Multi-Write
        9. 7.5.1.9 Write 2-Byte I2C Commands
    6. 7.6 BQ25773 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Snubber and Filter for Voltage Spike Damping
        2. 8.2.2.2 ACP-ACN Input Filter
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Power MOSFETs Selection
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Layout Example Reference Top View
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • REE|36
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 BQ25773 Registers

Table 7-10 lists the memory-mapped registers for the BQ25773 registers. All register offset addresses not listed in Table 7-10 should be considered as reserved locations and the register contents should not be modified.

Table 7-10 BQ25773 Registers
AddressAcronymRegister NameSection
0hREG0x00_ChargeOption0ChargeOption0()Go
1hREG0x01_ChargeOption0ChargeOption0()Go
2hREG0x02_CHARGE_CURRENTCHARGE_CURRENT()Go
4hREG0x04_CHARGE_VOLTAGECHARGE_VOLTAGE()Go
6hREG0x06_IIN_HOSTIIN_HOST()Go
8hREG0x08_VINDPMVINDPM()Go
AhREG0x0A_OTG_CURRENTOTG_CURRENT()Go
ChREG0x0C_OTG_VOLTAGEOTG_VOLTAGE()Go
EhREG0x0E_VSYS_MINVSYS_MIN()Go
10hREG0x10_ChargeProfileChargeProfile()Go
11hREG0x11_ChargeProfileChargeProfile()Go
12hREG0x12_GateDriveGateDrive()Go
13hREG0x13_GateDriveGateDrive()Go
14hREG0x14_ChargeOption5ChargeOption5()Go
15hREG0x15_ChargeOption5ChargeOption5()Go
16hREG0x16_AutoChargeAutoCharge()Go
17hREG0x17_AutoChargeAutoCharge()Go
18hREG0x18_ChargerStatus0ChargerStatus0()Go
19hREG0x19_ChargerStatus0ChargerStatus0()Go
1AhREG0x1A_ADC_VBATADC_VBAT()Go
1ChREG0x1C_ADC_PSYSADC_PSYS()Go
1EhREG0x1E_ADC_CMPIN_TRADC_CMPIN_TR()Go
20hREG0x20_ChargerStatus1ChargerStatus1()Go
21hREG0x21_ChargerStatus1ChargerStatus1()Go
22hREG0x22_Prochot_Status_RegisterProchot Status RegisterGo
23hREG0x23_Prochot_Status_RegisterProchot Status RegisterGo
24hREG0x24_IIN_DPMIIN_DPM()Go
26hREG0x26_ADC_VBUSADC_VBUS()Go
28hREG0x28_ADC_IBATADC_IBAT()Go
2AhREG0x2A_ADC_IINADC_IIN()Go
2ChREG0x2C_ADC_VSYSADC_VSYS()Go
2EhREG0x2E_Manufacture_IDManufacture IDGo
2FhREG0x2F_Device_IDDevice IDGo
30hREG0x30_ChargeOption1ChargeOption1()Go
31hREG0x31_ChargeOption1ChargeOption1()Go
32hREG0x32_ChargeOption2ChargeOption2()Go
33hREG0x33_ChargeOption2ChargeOption2()Go
34hREG0x34_ChargeOption3ChargeOption3()Go
35hREG0x35_ChargeOption3ChargeOption3()Go
36hREG0x36_ProchotOption0_RegisterProchotOption0 RegisterGo
37hREG0x37_ProchotOption0_RegisterProchotOption0 RegisterGo
38hREG0x38_ProchotOption1ProchotOption1()Go
39hREG0x39_ProchotOption1ProchotOption1()Go
3AhREG0x3A_ADCOptionADCOption()Go
3BhREG0x3B_ADCOptionADCOption()Go
3ChREG0x3C_ChargeOption4ChargeOption4()Go
3DhREG0x3D_ChargeOption4ChargeOption4()Go
3EhREG0x3E_Vmin_Active_ProtectionVmin Active Protection()Go
3FhREG0x3F_Vmin_Active_ProtectionVmin Active Protection()Go
60hREG0x60_AUTOTUNE_READAUTOTUNE_READ()Go
61hREG0x61_AUTOTUNE_READAUTOTUNE_READ()Go
62hREG0x62_AUTOTUNE_FORCEAUTOTUNE_FORCE()Go
63hREG0x63_AUTOTUNE_FORCEAUTOTUNE_FORCE()Go
64hREG0x64_GM_ADJUST_FORCEGM_ADJUST_FORCE()Go
65hREG0x65_GM_ADJUST_FORCEGM_ADJUST_FORCE()Go
80hREG0x80_VIRTUAL_CONTROLVIRTUAL_CONTROL()Go
81hREG0x81_VIRTUAL_CONTROLVIRTUAL_CONTROL()Go

Complex bit access types are encoded to fit into small table cells. Table 7-11 shows the codes that are used for access types in this section.

Table 7-11 BQ25773 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.6.1 REG0x00_ChargeOption0 Register (Address = 0h) [Reset = 0Eh]

REG0x00_ChargeOption0 is shown in Figure 7-22 and described in Table 7-12.

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Figure 7-22 REG0x00_ChargeOption0 Register
76543210
EN_CMP_LATCHVSYS_UVP_ENZEN_LEARNIADPT_GAINIBAT_GAINEN_LDOEN_IIN_DPMCHRG_INHIBIT
R/W-0hR/W-0hR/W-0hR/W-0hR/W-1hR/W-1hR/W-1hR/W-0h
Table 7-12 REG0x00_ChargeOption0 Register Field Descriptions
BitFieldTypeResetNotesDescription
7EN_CMP_LATCHR/W0hReset by:
REG_RESET		 Enable Latch of Independent Comparator. Comparator output with effective low. If enabled in PROCHOT profile PP_CMP=1b, STAT_COMP bit keep 1b after triggered until read by host and clear. host can clear CMPOUT pin by toggling this EN_CMP_LATCH bit 0b = No Latch
1b = Latch
6VSYS_UVP_ENZR/W0hReset by:
REG_RESET		 To disable system under voltage protection. 0b = Enable
1b = Disable
5EN_LEARNR/W0hReset by:
REG_RESET		 LEARN mode function enable: 0b = Disable
1b = Enable
4IADPT_GAINR/W0hReset by:
REG_RESET		 IADPT Amplifier Ratio
The ratio of voltage on IADPT and voltage across ACP and ACN. 0b = 20x
1b = 40x
3IBAT_GAINR/W1hReset by:
REG_RESET		 IBAT Amplifier Ratio
The ratio of voltage on IBAT and voltage across SRP and SRN 0b = 8x
1b = 64x
2EN_LDOR/W1hReset by:
REG_RESET		 LDO Mode Enable
When battery voltage is below VSYS_MIN(), the
charger is in pre-charge with LDO mode enabled. 0b = Disable LDO mode, BATFET fully ON when charge is enabled and VSYS_MIN() regulation is not effective unless VBAT<5V and system is regulated at 5V. When charge is disabled, BATFET is fully off and system is regulated at VBAT+160mV.
1b = Enable LDO mode, Precharge current is set by the lower setting of CHARGE_CURRENT()
and IPRECHG(). The system is regulated by the VSYS_MIN() register.
1EN_IIN_DPMR/W1hReset by:
REG_RESET		 IIN_DPM Enable
Host writes this bit to enable IIN_DPM regulation loop. When the IIN_DPM is disabled
by the charger (refer to IIN_DPM_AUTO_DISABLE), this bit goes LOW. Under OTG mode, this bit is also used to enable/disable IOTG regulation. 0b = Disable
1b = Enable
0CHRG_INHIBITR/W0hReset by:
REG_RESET		 Charge Inhibit
When this bit is 0, battery charging will start with valid values in the
CHARGE_VOLTAGE() and CHARGE_CURRENT(). 0b = Enable
1b = Inhibit

7.6.2 REG0x01_ChargeOption0 Register (Address = 1h) [Reset = E7h]

REG0x01_ChargeOption0 is shown in Figure 7-23 and described in Table 7-13.

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Figure 7-23 REG0x01_ChargeOption0 Register
76543210
EN_LWPWRWDTMR_ADJIIN_DPM_AUTO_DISABLEOTG_ON_CHRGOKEN_OOAPWM_FREQEN_BATOVP
R/W-1hR/W-3hR/W-0hR/W-0hR/W-1hR/W-1hR/W-1h
Table 7-13 REG0x01_ChargeOption0 Register Field Descriptions
BitFieldTypeResetNotesDescription
7EN_LWPWRR/W1hReset by:
REG_RESET		 Low Power Mode enable 0b = Disable Low Power Mode. Device in performance mode with battery only. The PROCHOT, IADPT/IBAT/PSYS and comparator follow corresponding register setting, REGN should be on with full capacity.
1b = Enable Low Power Mode. Device in low power mode with battery only for lowest quiescent current. The PROCHOT, discharge current monitor buffer, power monitor buffer and independent comparator are disabled. ADC is not available in Low Power Mode. Independent comparator can be enabled by setting EN_LWPWR_CMP to 1b. REGN can be enabled through EN_REGN_LWPWR=1b with 5mA current capability to save quiescent current.
6-5WDTMR_ADJR/W3hReset by:
REG_RESET		 WATCHDOG Timer Adjust
Set maximum delay between consecutive EC host write of charge voltage or charge current command.
If device does not receive a write on the CHARGE_VOLTAGE() or the CHARGE_CURRENT() within the watchdog time period, the charger will be suspended by setting the CHARGE_CURRENT() to 0 mA. After expiration, the timer will resume upon the write of CHARGE_CURRENT(), CHARGE_VOLTAGE() ,WDTMR_ADJ or WD_RST=1b. The charger will resume if the values are valid. 00b = Disable
01b = 5 sec
10b = 88 sec
11b = 175 sec
4IIN_DPM_AUTO_DISABLER/W0hReset by:
REG_RESET		 IIN_DPM Auto Disable
When CELL_BATPRES pin is LOW, the charger automatically disables the
IIN_DPM function by setting EN_IIN_DPM to 0. The host can enable
IIN_DPM function later by writing EN_IIN_DPM bit to 1. 0b = Disable
1b = Enable
3OTG_ON_CHRGOKR/W0hReset by:
REG_RESET		 Add OTG to CHRG_OK
Drive CHRG_OK to HIGH when the device is in OTG mode. 0b = Disable
1b = Enable
2EN_OOAR/W1hReset by:
REG_RESET		 Out-of-Audio Enable 0b = No Limit
1b = Set minimum PFM frequency above 20 kHz to avoid audio noise
1PWM_FREQR/W1h Switching Frequency Selection: Recommend 600kHz with 2.2uH, 800 kHz with 1.5µH. After charger POR, the MODE pin programming process will make one time change on frequency selection.
Note: Frequency is not allowed to change on the fly has to be changed when converter is HIZ. 0b = 800kHz
1b = 600kHz
0EN_BATOVPR/W1hReset by:
REG_RESET		 Enable BATOVP protection: 0b = Disable
1b = Enable

7.6.3 REG0x02_CHARGE_CURRENT Register (Address = 2h) [Reset = 0000h]

REG0x02_CHARGE_CURRENT is shown in Figure 7-24 and described in Table 7-14.

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I2C REG0x03=[15:8], I2C REG0x02=[7:0]

Figure 7-24 REG0x02_CHARGE_CURRENT Register
15141312111098
RESERVEDCHARGE_CURRENT
R-0hR/W-0h
76543210
CHARGE_CURRENTRESERVED
R/W-0hR-0h
Table 7-14 REG0x02_CHARGE_CURRENT Register Field Descriptions
BitFieldTypeResetNotesDescription
15-14RESERVEDR0h Reserved
13-3CHARGE_CURRENTR/W0hReset by:
REG_RESET
WATCHDOG		 Charge current setting with 5mΩ sense resistor (non-zero value lower than 128mA is treated as 128mA): Note when 2mΩ is chosen at RSNS_RSR=1b maximum charge current is clamped at 5DCh (30A with 20mA LSB). Under below scenarios CHARGE_CURRENT is reset to 0A:
1)BATCOC fault.
2)Charge Voltage() is written 0V
3)CELL_BATPRES going low(Battery removal)
4)STAT_AC is not valid(Adapter removal)
5)Watch dog event trigger
6) Autonomous charging get terminated (CHRG_STAT =111b)
7) Safety timer trigger
Note: Writing value beyond clamp high/low will actually set register to the clamp high/low value . POR: 0mA (0h)
Range: 0mA-16320mA (0h-7F8h)
Clamped High
Bit Step: 8mA
2-0RESERVEDR0h Reserved

7.6.4 REG0x04_CHARGE_VOLTAGE Register (Address = 4h) [Reset = 0000h]

REG0x04_CHARGE_VOLTAGE is shown in Figure 7-25 and described in Table 7-15.

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I2C REG0x05=[15:8], I2C REG0x04=[7:0]

Figure 7-25 REG0x04_CHARGE_VOLTAGE Register
15141312111098
RESERVEDCHARGE_VOLTAGE
R-0hR/W-0h
76543210
CHARGE_VOLTAGERESERVED
R/W-0hR-0h
Table 7-15 REG0x04_CHARGE_VOLTAGE Register Field Descriptions
BitFieldTypeResetNotesDescription
15RESERVEDR0h Reserved
14-2CHARGE_VOLTAGER/W0hWrite 0 to this register shall keep register value unchanged, and force CHARGE_CURRENT() to zero to disable charge.
Reset by:
REG_RESET		 Charge voltage setting
Note: Writing non-zero value beyond clamp high/low will actually set register to the clamp high/low value. When 0V is written, it should not change CHARGE_VOLTAGE() but reset CHARGE_CURRENT() to 0A POR: 0mV (0h)
Range: 5000mV-23000mV (4E2h-1676h)
Clamped Low
Clamped High
Bit Step: 4mV
Mode: 2s
8400mV
POR: 8400mV (834h) Mode: 3s
12600mV
POR: 12600mV (C4Eh) Mode: 4s
16800mV
POR: 16800mV (1068h) Mode: 5s
21000mV
POR: 21000mV (1482h)
1-0RESERVEDR0h Reserved

7.6.5 REG0x06_IIN_HOST Register (Address = 6h) [Reset = 0320h]

REG0x06_IIN_HOST is shown in Figure 7-26 and described in Table 7-16.

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I2C REG0x07=[15:8], I2C REG0x06=[7:0]

Figure 7-26 REG0x06_IIN_HOST Register
15141312111098
RESERVEDIIN_HOST
R-0hR/W-C8h
76543210
IIN_HOSTRESERVED
R/W-C8hR-0h
Table 7-16 REG0x06_IIN_HOST Register Field Descriptions
BitFieldTypeResetNotesDescription
15-11RESERVEDR0h Reserved
10-2IIN_HOSTR/WC8hReset by:
REG_RESET		 Maximum input current limit with 10mΩ sense resistor:
Note: Writing value beyond clamp high/low will actually set register to the clamp high/low value . POR: 5000mA (C8h)
Range: 400mA-8200mA (10h-148h)
Clamped Low
Clamped High
Bit Step: 25mA
1-0RESERVEDR0h Reserved

7.6.6 REG0x08_VINDPM Register (Address = 8h) [Reset = 0280h]

REG0x08_VINDPM is shown in Figure 7-27 and described in Table 7-17.

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I2C REG0x09=[15:8], I2C REG0x08=[7:0]

Figure 7-27 REG0x08_VINDPM Register
15141312111098
RESERVEDVINDPM
R-0hR/W-A0h
76543210
VINDPMRESERVED
R/W-A0hR-0h
Table 7-17 REG0x08_VINDPM Register Field Descriptions
BitFieldTypeResetNotesDescription
15-13RESERVEDR0h Reserved
12-2VINDPMR/WA0hReset by:
REG_RESET		 Input voltage limit:
Note: Writing value beyond clamp high/low will actually set register to the clamp high/low value . POR: 3200mV (A0h)
Range: 3200mV-27000mV (A0h-546h)
Clamped Low
Clamped High
Bit Step: 20mV
1-0RESERVEDR0h Reserved

7.6.7 REG0x0A_OTG_CURRENT Register (Address = Ah) [Reset = 01E0h]

REG0x0A_OTG_CURRENT is shown in Figure 7-28 and described in Table 7-18.

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I2C REG0x0B=[15:8], I2C REG0x0A=[7:0]

Figure 7-28 REG0x0A_OTG_CURRENT Register
15141312111098
RESERVEDOTG_CURRENT
R-0hR/W-78h
76543210
OTG_CURRENTRESERVED
R/W-78hR-0h
Table 7-18 REG0x0A_OTG_CURRENT Register Field Descriptions
BitFieldTypeResetNotesDescription
15-11RESERVEDR0h Reserved
10-2OTG_CURRENTR/W78hReset by:
REG_RESET		 OTG output current limit with 10mΩ Rac current sense:
Note: Writing value beyond clamp high/low will actually set register to the clamp high/low value . POR: 3000mA (78h)
Range: 100mA-3000mA (4h-78h)
Clamped Low
Clamped High
Bit Step: 25mA
1-0RESERVEDR0h Reserved

7.6.8 REG0x0C_OTG_VOLTAGE Register (Address = Ch) [Reset = 03E8h]

REG0x0C_OTG_VOLTAGE is shown in Figure 7-29 and described in Table 7-19.

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I2C REG0x0D=[15:8], I2C REG0x0C=[7:0]

Figure 7-29 REG0x0C_OTG_VOLTAGE Register
15141312111098
RESERVEDOTG_VOLTAGE
R-0hR/W-FAh
76543210
OTG_VOLTAGERESERVED
R/W-FAhR-0h
Table 7-19 REG0x0C_OTG_VOLTAGE Register Field Descriptions
BitFieldTypeResetNotesDescription
15-13RESERVEDR0h Reserved
12-2OTG_VOLTAGER/WFAhReset by:
REG_RESET		 OTG output voltage regulation:
Note: Writing value beyond clamp high/low will actually set register to the clamp high/low value . POR: 5000mV (FAh)
Range: 3000mV-5000mV (96h-FAh)
Clamped Low
Clamped High
Bit Step: 20mV
1-0RESERVEDR0h Reserved

7.6.9 REG0x0E_VSYS_MIN Register (Address = Eh) [Reset = 0528h]

REG0x0E_VSYS_MIN is shown in Figure 7-30 and described in Table 7-20.

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I2C REG0x0F=[15:8], I2C REG0x0E=[7:0]

Figure 7-30 REG0x0E_VSYS_MIN Register
15141312111098
RESERVEDVSYS_MIN
R-0hR/W-528h
76543210
VSYS_MIN
R/W-528h
Table 7-20 REG0x0E_VSYS_MIN Register Field Descriptions
BitFieldTypeResetNotesDescription
15-13RESERVEDR0h Reserved
12-0VSYS_MINR/W528hReset by:
REG_RESET		 Minimum system voltage configuration register
Note: Writing value beyond clamp high/low will actually set register to the clamp high/low value . POR: 6600mV (528h)
Range: 5000mV-21000mV (3E8h-1068h)
Clamped Low
Clamped High
Bit Step: 5mV
Mode: 2s
6600mV Mode: 3s
9200mV
POR: 9200mV (730h) Mode: 4s
12300mV
POR: 12300mV (99Ch) Mode: 5s
15400mV
POR: 15400mV (C08h)

7.6.10 REG0x10_ChargeProfile Register (Address = 10h) [Reset = 20h]

REG0x10_ChargeProfile is shown in Figure 7-31 and described in Table 7-21.

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Figure 7-31 REG0x10_ChargeProfile Register
76543210
ITERM
R/W-20h
Table 7-21 REG0x10_ChargeProfile Register Field Descriptions
BitFieldTypeResetNotesDescription
7-0ITERMR/W20hReset by:
REG_RESET		 Termination current setting with 5mΩ sense resistor:
Note: Writing value beyond clamp high/low will actually set register to the clamp high/low value . POR: 256mA (20h)
Range: 128mA-2016mA (10h-FCh)
Clamped Low
Clamped High
Bit Step: 8mA

7.6.11 REG0x11_ChargeProfile Register (Address = 11h) [Reset = 30h]

REG0x11_ChargeProfile is shown in Figure 7-32 and described in Table 7-22.

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Figure 7-32 REG0x11_ChargeProfile Register
76543210
IPRECHG
R/W-30h
Table 7-22 REG0x11_ChargeProfile Register Field Descriptions
BitFieldTypeResetNotesDescription
7-0IPRECHGR/W30hReset by:
REG_RESET		 Maximum precharge current clamp setting with 5mΩ sense resistor(The lower setting of CHARGE_CURRENT() and IPRECHG determine the practical precharge current when VBAT< VSYS_MIN()): Note when 2mΩ sense resistor is chosen RSNS_RSR=1b, then the IPRECHG() upper clamp should be 66H to limit BATFET thermal dissipation.
Note: Writing value beyond clamp high/low will actually set register to the clamp high/low value . POR: 384mA (30h)
Range: 128mA-2016mA (10h-FCh)
Clamped Low
Clamped High
Bit Step: 8mA

7.6.12 REG0x12_GateDrive Register (Address = 12h) [Reset = 6Ch]

REG0x12_GateDrive is shown in Figure 7-33 and described in Table 7-23.

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Figure 7-33 REG0x12_GateDrive Register
76543210
HIDRV2_STATLODRV2_STATVSYS_REG_SLOWRESERVED
R/W-3hR/W-3hR/W-0hR-0h
Table 7-23 REG0x12_GateDrive Register Field Descriptions
BitFieldTypeResetNotesDescription
7-5HIDRV2_STATR/W3h Suggested HIDRV2 HS MOSFET gate drive strength adjustment for both turn on and turn off: 000b = Scale0 (Vgs=4.5V typical Qg range:0-5nC)
001b = Scale1(Vgs=4.5V typical Qg range:5-13nC )
010b = Scale2 (Vgs=4.5V typical Qg range:13-21nC )
011b = Scale3(Vgs=4.5V typical Qg range:21-29nC)
100b = Scale4 (Vgs=4.5V typical Qg range:29-37nC)
101b = Scale5(Vgs=4.5V typical Qg range:37-45nC)
110b = Scale6 (Vgs=4.5V typical Qg range:45-53nC)
111b = Scale7(Vgs=4.5V typical Qg range: >53nC)
4-2LODRV2_STATR/W3h Suggested LODRV2 LS MOSFET gate drive strength adjustment for both turn on and turn off: 000b = Scale0 (Vgs=4.5V typical Qg range:0-5nC)
001b = Scale1(Vgs=4.5V typical Qg range:5-13nC )
010b = Scale2 (Vgs=4.5V typical Qg range:13-21nC )
011b = Scale3(Vgs=4.5V typical Qg range:21-29nC)
100b = Scale4 (Vgs=4.5V typical Qg range:29-37nC)
101b = Scale5(Vgs=4.5V typical Qg range:37-45nC)
110b = Scale6 (Vgs=4.5V typical Qg range:45-53nC)
111b = Scale7(Vgs=4.5V typical Qg range: >53nC)
1VSYS_REG_SLOWR/W0h System regulation loop bandwidth slow down to reduce input current overshoot during load transient: 0b = Disable
1b = Enable
0RESERVEDR0h Reserved

7.6.13 REG0x13_GateDrive Register (Address = 13h) [Reset = 6Ch]

REG0x13_GateDrive is shown in Figure 7-34 and described in Table 7-24.

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Figure 7-34 REG0x13_GateDrive Register
76543210
HIDRV1_STATLODRV1_STATRESERVEDBATOVP_EXTEND
R/W-3hR/W-3hR-0hR/W-0h
Table 7-24 REG0x13_GateDrive Register Field Descriptions
BitFieldTypeResetNotesDescription
7-5HIDRV1_STATR/W3h Suggested HIDRV1_A and HIDRV1_B HS MOSFET gate drive strength adjustment for both turn on and turn off: 000b = Scale0 (Vgs=4.5V typical Qg range:0-5nC)
001b = Scale1(Vgs=4.5V typical Qg range:5-13nC )
010b = Scale2 (Vgs=4.5V typical Qg range:13-21nC )
011b = Scale3(Vgs=4.5V typical Qg range:21-29nC)
100b = Scale4 (Vgs=4.5V typical Qg range:29-37nC)
101b = Scale5(Vgs=4.5V typical Qg range:37-45nC)
110b = Scale6 (Vgs=4.5V typical Qg range:45-53nC)
111b = Scale7(Vgs=4.5V typical Qg range: >53nC)
4-2LODRV1_STATR/W3h Suggested LODRV1_A and LODRV1_B LS MOSFET gate drive strength adjustment for both turn on and turn off: 000b = Scale0 (Vgs=4.5V typical Qg range:0-5nC)
001b = Scale1(Vgs=4.5V typical Qg range:5-13nC )
010b = Scale2 (Vgs=4.5V typical Qg range:13-21nC )
011b = Scale3(Vgs=4.5V typical Qg range:21-29nC)
100b = Scale4 (Vgs=4.5V typical Qg range:29-37nC)
101b = Scale5(Vgs=4.5V typical Qg range:37-45nC)
110b = Scale6 (Vgs=4.5V typical Qg range:45-53nC)
111b = Scale7(Vgs=4.5V typical Qg range: >53nC)
1RESERVEDR0h Reserved
0BATOVP_EXTENDR/W0h Enable BATOVP for both charge enable and disable scenarios including AC+battery and battery only.
0b: BATOVP is only active when charge is enabled(BATFET is turned on) when EN_BATOVP=1b
1b: BATOVP is active as long as EN_BATOVP=1b, no matter charge is enabled or not(BATFET is on or off) 0b = Disable
1b = Enable

7.6.14 REG0x14_ChargeOption5 Register (Address = 14h) [Reset = 85h]

REG0x14_ChargeOption5 is shown in Figure 7-35 and described in Table 7-25.

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Figure 7-35 REG0x14_ChargeOption5 Register
76543210
SINGLE_DUAL_TRANS_THFORCE_SINGLEPH_ADD_DEGPH_DROP_DEG
R/W-4hR/W-0hR/W-1hR/W-1h
Table 7-25 REG0x14_ChargeOption5 Register Field Descriptions
BitFieldTypeResetNotesDescription
7-5SINGLE_DUAL_TRANS_THR/W4hReset by:
REG_RESET		 Buck mode single to dual phase transition threshold adjustment based on output load current: (When Quasi dual phase is chosen at MODE pin programming) Note from dual phase to single phase transition the load current threshold is 1A lower than this configuration as hysteresis. 000b = Force Dual Phase Operation
001b = 3A
010b = 4A
011b = 5A
100b = 6A
101b = 7A
110b = 8A
111b = 9A
4FORCE_SINGLER/W0hReset by:
REG_RESET		 Force single phase operation under buck mode when quasi dual phase is chosen through MODE pin programming: 0b = Automatically transit to dual phase based on SINGLE_DUAL_TRANS_TH threshold option
1b = Force Single Phase under buck mode
3-2PH_ADD_DEGR/W1hReset by:
REG_RESET		 Adjust single phase to dual phase( phase adding transition) deglitch time: 00b = 0.727us(Min)/1.7us(Typ)/2.67us(Max)
01b = 2.91us(Min)/5.5us(Typ)/8us(Max)
10b = 11.6us(Min)/20us(Typ)/29.3us(Max)
11b = 46.6us(Min)/86us(Typ)/115us(Max)
1-0PH_DROP_DEGR/W1hReset by:
REG_RESET		 Adjust dual phase to single phase( phase dropping transition) deglitch time: 00b = 70us(Min)/93us(Typ)/115us(Max)
01b = 1.12ms(Min)/1.5ms(Typ)/1.82ms(Max)
10b = 8.94ms(Min)/11ms(Typ)/1.46ms(Max)
11b = 71.5ms(Min)/94ms(Typ)/117ms(Max)

7.6.15 REG0x15_ChargeOption5 Register (Address = 15h) [Reset = 06h]

REG0x15_ChargeOption5 is shown in Figure 7-36 and described in Table 7-26.

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Figure 7-36 REG0x15_ChargeOption5 Register
76543210
PTM_EXIT_LIGHT_LOADWD_RSTCMPIN_TR_SELECTREGN_EXTEN_REGN_LWPWRBATCOC_CONFIGRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-3hR-0h
Table 7-26 REG0x15_ChargeOption5 Register Field Descriptions
BitFieldTypeResetNotesDescription
7PTM_EXIT_LIGHT_LOADR/W0hReset by:
REG_RESET		 Enable PTM auto exit under light load: 0b = Disable
1b = Enable
6WD_RSTR/W0hReset by:
REG_RESET		 Reset watch dog timer control: 0b = Normal
1b = Reset(bit goes back to 0 after timer reset)
5CMPIN_TR_SELECTR/W0hReset by:
REG_RESET		 CPMIN_TS pin function selection: 0b = CPMIN function
1b = TREG function
4REGN_EXTR/W0hReset by:
REG_RESET		 Enable external 5V overdrive for REGN: 0b = Disabled external 5V over drive
1b = Enable external 5V over drive
3EN_REGN_LWPWRR/W0hReset by:
REG_RESET		 Enable REGN with scale down current 5mA capability under battery only and low power mode: 0b = Disabled REGN under battery only low power mode
1b = Enable REGN under battery only low power mode
2-1BATCOC_CONFIGR/W3hReset by:
REG_RESET		 Disable BATCOC and configure BATCOC thresholds across SRP-SRN: 00b = Disable
01b = 50mV
10b = 75mV
11b = 100mV
0RESERVEDR0h Reserved

7.6.16 REG0x16_AutoCharge Register (Address = 16h) [Reset = C2h]

REG0x16_AutoCharge is shown in Figure 7-37 and described in Table 7-27.

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Figure 7-37 REG0x16_AutoCharge Register
76543210
EN_TMR2XEN_CHG_TMREN_TREGPP_THERMALSTAT_THERMALTHERMAL_DEGACOV_ADJ
R/W-1hR/W-1hR/W-0hR/W-0hR-0hR/W-0hR/W-2h
Table 7-27 REG0x16_AutoCharge Register Field Descriptions
BitFieldTypeResetNotesDescription
7EN_TMR2XR/W1hReset by:
REG_RESET		 Charge Safety Timer speed control: (Note changing the state of EN_TMR2X only impacts the rate at which the counter is counting and has no effect on any existing accumulated count) 0b = Timer always counts normally
1b = Timer slowed by 2x during VINDPM/IINDPM/TREG regulation
6EN_CHG_TMRR/W1hReset by:
REG_RESET
WATCHDOG		 Enable charge safety timer: 0b = Disable
1b = Enable
5EN_TREGR/W0hReset by:
REG_RESET		 Enable temperature regulation function and pull down CMPOUT pin to GND if CMPIN_TR_SELECT=1b. If CMPIN_TR_SELECT=0b, then EN_TREG will not be effective. 0b = Disable temperature regulation function
1b = Enable temperature regulation function
4PP_THERMALR/W0hReset by:
REG_RESET		 Enable temperature regulation(TREG) for PROCHOT profile. 0b = Disable
1b = Enable
3STAT_THERMALR0hReset by:
REG_RESET		 PROCHOT profile status bit for TREG thermal overheat (CMPIN_TR< 1.1V). The status is latched until a read from host. 0b = Not Triggered
1b = Triggered
2THERMAL_DEGR/W0hReset by:
REG_RESET		 Adjust TREG thermal deglitch time to trigger prochot profile pull down pulse. 0b = 0.76sec(min)/0.965sec(Typ.)/1.17sec(max)
1b = 95.3ms(min)/121ms(Typ.)/146ms(max)
1-0ACOV_ADJR/W2hReset by:
REG_RESET		 ACOV protection threshold adjustment: 00b = 20V(15V SPR)
01b = 25V(20V SPR )
10b = 33V(28V EPR )
11b = 41V(36V EPR)

7.6.17 REG0x17_AutoCharge Register (Address = 17h) [Reset = 01h]

REG0x17_AutoCharge is shown in Figure 7-38 and described in Table 7-28.

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Figure 7-38 REG0x17_AutoCharge Register
76543210
EN_AUTO_CHGCHRG_OK_INTVRECHGCHG_TMR
R/W-0hR/W-0hR/W-0hR/W-1h
Table 7-28 REG0x17_AutoCharge Register Field Descriptions
BitFieldTypeResetNotesDescription
7EN_AUTO_CHGR/W0hReset by:
REG_RESET		 Automatic charge control (recharge and terminate battery charging automatically): 0b = Disable
1b = Enable
6CHRG_OK_INTR/W0hReset by:
REG_RESET		 Enable CHRG_OK pin for interrupt function: 0b = Disable(CHRG_OK pin is not pulled low when CHRG_STAT bits changes)
1b = Enable(CHRG_OK pin is pulled low for minimum 256us when CHRG_STAT bits changes)
5-2VRECHGR/W0hReset by:
REG_RESET		 Battery automatic recharge threshold below CHARGE_VOLTAGE(): POR: 50mV (0h)
Range: 50mV-800mV (0h-Fh)
Bit Step: 50mV
Offset: 50mV
Mode: 2s
200mV
POR: 200mV (3h) Mode: 3s
300mV
POR: 300mV (5h) Mode: 4s
400mV
POR: 400mV (7h) Mode: 5s
500mV
POR: 500mV (9h)
1-0CHG_TMRR/W1hReset by:
REG_RESET		 Automatic Charge Safety Timer control: 00b = 5hr
01b = 8hr
10b = 12hr
11b = 24hr

7.6.18 REG0x18_ChargerStatus0 Register (Address = 18h) [Reset = 00h]

REG0x18_ChargerStatus0 is shown in Figure 7-39 and described in Table 7-29.

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Figure 7-39 REG0x18_ChargerStatus0 Register
76543210
FAULT_BATOVPRESERVEDFAULT_OCPRESERVEDFAULT_REGNRESERVED
R-0hR-0hR-0hR-0hR-0hR-0h
Table 7-29 REG0x18_ChargerStatus0 Register Field Descriptions
BitFieldTypeResetNotesDescription
7FAULT_BATOVPR0hReset by:
REG_RESET		 The status are latched until a read from host, , if the fault still exist during host read this bit should be kept at 1b. However after host read fault status one time, this bit will be automatically reset when the original fault is cleared. In this way host doesn't need to read again to clear this fault bit after fault is removed. 0b = No Fault
1b = Fault
6RESERVEDR0h Reserved
5FAULT_OCPR0hReset by:
REG_RESET		 The status are latched until a read from host, if the fault still exist during host read this bit should be kept at 1b. However after host read fault status one time, this bit will be automatically reset when the original fault is cleared. 0b = No Fault
1b = Fault
4RESERVEDR0h Reserved
3FAULT_REGNR0hReset by:
REG_RESET		 The status are latched until a read from host, , if the fault still exist during host read this bit should be kept at 1b. However after host read fault status one time, this bit will be automatically reset when the original fault is cleared. In this way host doesn't need to read again to clear this fault bit after fault is removed. 0b = No Fault
1b = Fault
2-0RESERVEDR0h Reserved

7.6.19 REG0x19_ChargerStatus0 Register (Address = 19h) [Reset = 00h]

REG0x19_ChargerStatus0 is shown in Figure 7-40 and described in Table 7-30.

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ChargeStatus0()

Figure 7-40 REG0x19_ChargerStatus0 Register
76543210
CHRG_STATCHG_TMR_STATTREG_STATMODE_STAT
R-0hR-0hR-0hR-0h
Table 7-30 REG0x19_ChargerStatus0 Register Field Descriptions
BitFieldTypeResetNotesDescription
7-5CHRG_STATR0h Charge Cycle Status 000b = Not Charging
001b = Trickle Charge (VBAT<VBAT_SHORT)
010b = Pre-Charge (VBAT<VSYS_MIN)
011b = Fast Charge(CC mode)
100b = Fast Charge(CV mode)
101b = Reserve1
110b = Reserve2
111b = Charge Termination Done
4CHG_TMR_STATR0hReset by:
REG_RESET		 Charge safety timer status 0b = Normal
1b = Charge safety timer expired
3TREG_STATR0hReset by:
REG_RESET		 Temperature regulation status 0b = Not in temperature regulation(TREG)
1b = In temperature regulation(TREG)
2-0MODE_STATR0h MODE pin program status 000b = Quasi Dual Phase/Normal Compensation/Fsw-600kHz
001b = Quasi Dual Phase/Normal Compensation/Fsw-800kHz
010b = Quasi Dual Phase/Slow Compensation/Fsw-600kHz
011b = Quasi Dual Phase/Slow Compensation/Fsw-800kHz
100b = NA/Normal Compensation/Fsw-600kHz
101b = NA/Normal Compensation/Fsw-800kHz
110b = NA/Slow Compensation/Fsw-600kHz
111b = NA/Slow Compensation/Fsw-800kHz

7.6.20 REG0x1A_ADC_VBAT Register (Address = 1Ah) [Reset = 0000h]

REG0x1A_ADC_VBAT is shown in Figure 7-41 and described in Table 7-31.

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I2C REG0x1B=[15:8], I2C REG0x1A=[7:0]

Figure 7-41 REG0x1A_ADC_VBAT Register
15141312111098
ADC_VBAT
R-0h
76543210
ADC_VBAT
R-0h
Table 7-31 REG0x1A_ADC_VBAT Register Field Descriptions
BitFieldTypeResetNotesDescription
15-0ADC_VBATR0hReset by:
REG_RESET		 VBAT ADC reading: POR: 0mV (0h)
Format: 2s Complement
Range: 0mV-32767mV (0h-7FFFh)
Clamped Low
Bit Step: 1mV

7.6.21 REG0x1C_ADC_PSYS Register (Address = 1Ch) [Reset = 0000h]

REG0x1C_ADC_PSYS is shown in Figure 7-42 and described in Table 7-32.

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I2C REG0x1D=[15:8], I2C REG0x1C=[7:0]

Figure 7-42 REG0x1C_ADC_PSYS Register
15141312111098
ADC_PSYS
R-0h
76543210
ADC_PSYS
R-0h
Table 7-32 REG0x1C_ADC_PSYS Register Field Descriptions
BitFieldTypeResetNotesDescription
15-0ADC_PSYSR0hClamp at 3.2V
Reset by:
REG_RESET		 System Power PSYS ADC reading: POR: 0mV (0h)
Range: 0mV-8191mV (0h-1FFFh)
Clamped High
Bit Step: 1mV

7.6.22 REG0x1E_ADC_CMPIN_TR Register (Address = 1Eh) [Reset = 0000h]

REG0x1E_ADC_CMPIN_TR is shown in Figure 7-43 and described in Table 7-33.

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I2C REG0x1F=[15:8], I2C REG0x1E=[7:0]

Figure 7-43 REG0x1E_ADC_CMPIN_TR Register
15141312111098
ADC_CMPIN_TR
R-0h
76543210
ADC_CMPIN_TR
R-0h
Table 7-33 REG0x1E_ADC_CMPIN_TR Register Field Descriptions
BitFieldTypeResetNotesDescription
15-0ADC_CMPIN_TRR0hPin abs max = 5.5V
Reset by:
REG_RESET		 CMPIN_TR pin voltage ADC reading: POR: 0mV (0h)
Range: 0mV-8191mV (0h-1FFFh)
Clamped High
Bit Step: 1mV

7.6.23 REG0x20_ChargerStatus1 Register (Address = 20h) [Reset = 00h]

REG0x20_ChargerStatus1 is shown in Figure 7-44 and described in Table 7-34.

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Figure 7-44 REG0x20_ChargerStatus1 Register
76543210
FAULT_ACOVFAULT_BATDOCFAULT_ACOCFAULT_SYSOVPFAULT_VSYS_UVPFAULT_FRC_CONV_OFFFAULT_OTG_OVPFAULT_OTG_UVP
R-0hR-0hR-0hR/W-0hR/W-0hR-0hR-0hR-0h
Table 7-34 REG0x20_ChargerStatus1 Register Field Descriptions
BitFieldTypeResetNotesDescription
7FAULT_ACOVR0hReset by:
REG_RESET		 The faults are latched until a read from host, if the fault still exist during host read this bit should be kept at 1b. However after host read fault status one time, this bit will be automatically reset when the original fault is cleared. In this way host doesn't need to read again to clear this fault bit after fault is removed. 0b = No Fault
1b = Fault
6FAULT_BATDOCR0hReset by:
REG_RESET		 The faults are latched until a read from host, if the fault still exist during host read this bit should be kept at 1b. However after host read fault status one time, this bit will be automatically reset when the original fault is cleared. In this way host doesn't need to read again to clear this fault bit after fault is removed. 0b = No Fault
1b = Fault
5FAULT_ACOCR0hReset by:
REG_RESET		 The faults are latched until a read from host, if the fault still exist during host read this bit should be kept at 1b. However after host read fault status one time, this bit will be automatically reset when the original fault is cleared. In this way host doesn't need to read again to clear this fault bit after fault is removed. 0b = No Fault
1b = Fault
4FAULT_SYSOVPR/W0hReset by:
REG_RESET		 SYSOVP fault status and Clear
When the SYSOVP occurs, this bit is set HIGH. As long as this bit is high, the converter is disabled. After the SYSOVP is removed, the user must write a 0 to this bit or unplug the adapter to clear the SYSOVP condition to enable the converter again. 0b = No Fault
1b = Fault
3FAULT_VSYS_UVPR/W0hReset by:
REG_RESET		 VSYS_UVP fault status and clear. It is latched until a clear from host by writing this bit to 0.
As long as this bit is high, the converter is disabled. After the VSYS_UVP is removed, the user must write a 0 to this bit or unplug the adapter to clear the VSYS_UVP condition to enable the converter again. 0b = No Fault
1b = Fault
2FAULT_FRC_CONV_OFFR0hReset by:
REG_RESET		 Force converter off when independent comparator is triggered low effective. The faults are latched until a read from host, if the fault still exist during host read this bit should be kept at 1b. However after host read fault status one time, this bit will be automatically reset when the original fault is cleared. In this way host doesn't need to read again to clear this fault bit after fault is removed. 0b = No Fault
1b = Fault
1FAULT_OTG_OVPR0hReset by:
REG_RESET		 The faults are latched until a read from host, if the fault still exist during host read this bit should be kept at 1b. However after host read fault status one time, this bit will be automatically reset when the original fault is cleared. In this way hos 0b = No Fault
1b = Fault
0FAULT_OTG_UVPR0hReset by:
REG_RESET		 The faults are latched until a read from host, if the fault still exist during host read this bit should be kept at 1b. However after host read fault status one time, this bit will be automatically reset when the original fault is cleared. In this way host doesn't need to read again to clear this fault bit after fault is removed. 0b = No Fault
1b = Fault

7.6.24 REG0x21_ChargerStatus1 Register (Address = 21h) [Reset = 00h]

REG0x21_ChargerStatus1 is shown in Figure 7-45 and described in Table 7-35.

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Figure 7-45 REG0x21_ChargerStatus1 Register
76543210
STAT_ACICO_DONEIN_VAPIN_VINDPMIN_IIN_DPMFAULT_SC_VBUSACPFAULT_BATCOCIN_OTG
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 7-35 REG0x21_ChargerStatus1 Register Field Descriptions
BitFieldTypeResetNotesDescription
7STAT_ACR0hReset by:
REG_RESET		 Input source status, STAT_AC is active as long as valid VBUS source exist 0b = Not Present
1b = Present
6ICO_DONER0hReset by:
REG_RESET		 After the ICO routine is successfully executed, the bit goes 1. 0b = Not Complete
1b = Complete
5IN_VAPR0hReset by:
REG_RESET		 Digital status bit indicates VAP has been enabled(1) or disabled(0). The enable of VAP mode only follows the host command, which is not blocked by any status of /PROCHOT. The exit of VAP mode also follows the host command, except that any faults will exit VAP mode automatically. STAT_EXIT_VAP becomes 1 which will pull low /PROCHOT until host clear.
The host can enable VAP by setting EN_OTG pin high and OTG_VAP_MODE=0b, disable VAP by setting either EN_OTG pin low or OTG_VAP_MOD=1b. When IN_VAP bit goes 0->1, charger should disable VinDPM, IIN_DPM, ILIM pin, disable PP_ACOK if it is enabled, enable PP_VSYS if it is disabled. When IN_VAP bit goes 1->0, charger should enable VinDPM, IIN_DPM, ILIM pin 0b = Not Operated
1b = Operated
4IN_VINDPMR0hReset by:
REG_RESET		 VINDPM/ VOTG Status 0b = Charger is not in VINDPM during forward mode, or voltage
regulation during OTG mode
1b = Charger is in VINDPM during forward mode, or voltage
regulation during OTG mode
3IN_IIN_DPMR0hReset by:
REG_RESET		 IIN_DPM / IOTG Status 0b = Not In IIN_DPM
1b = In IIN_DPM
2FAULT_SC_VBUSACPR0hReset by:
REG_RESET		 The faults are latched until a read from host, if the fault still exist during host read this bit should be kept at 1b. However after host read fault status one time, this bit will be automatically reset when the original fault is cleared. In this way host doesn't need to read again to clear this fault bit after fault is removed. 0b = No Fault
1b = Fault
1FAULT_BATCOCR0hReset by:
REG_RESET		 The faults are latched until a read from host after 1 second after triggering. To recover charge, EC also need to re-write non zero value into CHARGE_CURRENT() register. 0b = No Fault
1b = Fault
0IN_OTGR0hReset by:
REG_RESET		 OTG 0b = Not In OTG
1b = In OTG

7.6.25 REG0x22_Prochot_Status_Register (Address = 22h) [Reset = 00h]

REG0x22_Prochot_Status_Register is shown in Figure 7-46 and described in Table 7-36.

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Figure 7-46 REG0x22_Prochot_Status_Register
76543210
STAT_VINDPMSTAT_COMPSTAT_ICRITSTAT_INOMSTAT_IDCHG1STAT_VSYSSTAT_BATTERY_REMOVALSTAT_ADAPTER_REMOVAL
R/W-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 7-36 REG0x22_Prochot_Status_Register Field Descriptions
BitFieldTypeResetNotesDescription
7STAT_VINDPMR/W0hReset by:
REG_RESET		 PROCHOT Profile VINDPM status bit, once triggered 1b, PROCHOT pin is low until host writes this status bit to 0b when PP_VINDPM = 1b. 0b = Not Triggered
1b = Triggered
6STAT_COMPR0hReset by:
REG_RESET		 The status is latched until a read from host. 0b = Not Triggered
1b = Triggered
5STAT_ICRITR0hReset by:
REG_RESET		 The status is latched until a read from host. 0b = Not Triggered
1b = Triggered
4STAT_INOMR0hReset by:
REG_RESET		 The status is latched until a read from host. 0b = Not Triggered
1b = Triggered
3STAT_IDCHG1R0hReset by:
REG_RESET		 The status is latched until a read from host. 0b = Not Triggered
1b = Triggered
2STAT_VSYSR0hReset by:
REG_RESET		 The status is latched until a read from host. 0b = Not Triggered
1b = Triggered
1STAT_BATTERY_REMOVALR0hReset by:
REG_RESET		 The status is latched until a read from host. 0b = Not Triggered
1b = Triggered
0STAT_ADAPTER_REMOVALR0hReset by:
REG_RESET		 The status is latched until a read from host. 0b = Not Triggered
1b = Triggered

7.6.26 REG0x23_Prochot_Status_Register (Address = 23h) [Reset = 38h]

REG0x23_Prochot_Status_Register is shown in Figure 7-47 and described in Table 7-37.

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Figure 7-47 REG0x23_Prochot_Status_Register
76543210
RESERVEDEN_PROCHOT_EXTPROCHOT_WIDTHPROCHOT_CLEARTSHUTSTAT_VAP_FAILSTAT_EXIT_VAP
R-0hR/W-0hR/W-3hR/W-1hR-0hR/W-0hR/W-0h
Table 7-37 REG0x23_Prochot_Status_Register Field Descriptions
BitFieldTypeResetNotesDescription
7RESERVEDR0h Reserved
6EN_PROCHOT_EXTR/W0hReset by:
REG_RESET		 PROCHOT Pulse Extension Enable. When pulse extension is enabled, keep the PROCHOT pin voltage LOW until host writes PROCHOT_CLEAR= 0b. 0b = Disable
1b = Enable
5-4PROCHOT_WIDTHR/W3hReset by:
REG_RESET		 PROCHOT Pulse Width when
EN_PROCHOT_EXT = 0b 00b = 83ms(min)/100ms(Typ.)/117ms(max)
01b = 42ms(min)/50ms(Typ.)/58ms(max)
10b = 5ms(min)/6.15ms(Typ.)/7.3ms(max)
11b = 10ms(min)/12.5ms(Typ.)/15ms(max)
3PROCHOT_CLEARR/W1hReset by:
REG_RESET		 PROCHOT Pulse Clear.
Clear PROCHOT pulse when EN_PROCHOT_EXT=0b. 0b = Clear PROCHOT pulse and drive /PROCHOT pin HIGH
1b = Idle
2TSHUTR0hReset by:
REG_RESET		 TSHUT trigger 0b = Not Triggered
1b = Triggered
1STAT_VAP_FAILR/W0hReset by:
REG_RESET		 This status bit reports a failure to load VBUS 7 consecutive times in VAP mode, which indicates the battery voltage might be not high enough to enter VAP mode, or the VAP loading current settings are too high. 0b = Not is VAP failure
1b = In VAP failure, the charger exits VAP mode, and latches off until the host writes this bit to 0.
0STAT_EXIT_VAPR/W0hReset by:
REG_RESET		 When the charger is operated in VAP mode, it can exit VAP by either being disabled through host, or there is any charger faults. 0b = PROCHOT_EXIT_VAP is not active
1b = PROCHOT_EXIT_VAP is active, PROCHOT pin is low until host writes this status bit to 0

7.6.27 REG0x24_IIN_DPM Register (Address = 24h) [Reset = 0320h]

REG0x24_IIN_DPM is shown in Figure 7-48 and described in Table 7-38.

Return to the Summary Table.

I2C REG0x25=[15:8], I2C REG0x24=[7:0]

Figure 7-48 REG0x24_IIN_DPM Register
15141312111098
RESERVEDIIN_DPM
R-0hR-C8h
76543210
IIN_DPMRESERVED
R-C8hR-0h
Table 7-38 REG0x24_IIN_DPM Register Field Descriptions
BitFieldTypeResetNotesDescription
15-11RESERVEDR0h Reserved
10-2IIN_DPMRC8hReset by:
REG_RESET		 Input current setting with 10mΩ sense resistor: POR: 5000mA (C8h)
Range: 400mA-8200mA (10h-148h)
Clamped Low
Clamped High
Bit Step: 25mA
1-0RESERVEDR0h Reserved

7.6.28 REG0x26_ADC_VBUS Register (Address = 26h) [Reset = 0000h]

REG0x26_ADC_VBUS is shown in Figure 7-49 and described in Table 7-39.

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I2C REG0x27=[15:8], I2C REG0x26=[7:0]

Figure 7-49 REG0x26_ADC_VBUS Register
15141312111098
ADC_VBUS
R-0h
76543210
ADC_VBUS
R-0h
Table 7-39 REG0x26_ADC_VBUS Register Field Descriptions
BitFieldTypeResetNotesDescription
15-0ADC_VBUSR0hReset by:
REG_RESET		 VBUS ADC reading:
(Note: When VBUS plugged in before converter starts up , VBUS ADC channel should execute one time to read the no-load VBUS voltage and save the value into ADC_VBUS()) POR: 0mV (0h)
Format: 2s Complement
Range: 0mV-65534mV (0h-7FFFh)
Clamped Low
Bit Step: 2mV

7.6.29 REG0x28_ADC_IBAT Register (Address = 28h) [Reset = 0000h]

REG0x28_ADC_IBAT is shown in Figure 7-50 and described in Table 7-40.

Return to the Summary Table.

I2C REG0x29=[15:8], I2C REG0x28=[7:0]

Figure 7-50 REG0x28_ADC_IBAT Register
15141312111098
ADC_IBAT
R-0h
76543210
ADC_IBAT
R-0h
Table 7-40 REG0x28_ADC_IBAT Register Field Descriptions
BitFieldTypeResetNotesDescription
15-0ADC_IBATR0hReset by:
REG_RESET		 IBAT ADC reading with 5mΩ sense resistor: Note the charger only measures discharging current (negative voltage) under battery only or OTG modes, and only measure charging current(positive voltage) when valid adapter is plugged in POR: 0mA (0h)
Format: 2s Complement
Range: -32768mA-32767mA (8000h-7FFFh)
Bit Step: 1mA

7.6.30 REG0x2A_ADC_IIN Register (Address = 2Ah) [Reset = 0000h]

REG0x2A_ADC_IIN is shown in Figure 7-51 and described in Table 7-41.

Return to the Summary Table.

I2C REG0x2B=[15:8], I2C REG0x2A=[7:0]

Figure 7-51 REG0x2A_ADC_IIN Register
15141312111098
ADC_IIN
R-0h
76543210
ADC_IIN
R-0h
Table 7-41 REG0x2A_ADC_IIN Register Field Descriptions
BitFieldTypeResetNotesDescription
15-0ADC_IINR0hReset by:
REG_RESET		 IIN ADC reading with 10mΩ sense resistor: current flowing from the adapter to the converter (like in forward mode) is represented as positive and current flowing to the adapter (like in OTG mode) is negative. POR: 0mA(0h)
Format: 2s Complement
Range: -16384mA - 16383.5mA (8000h-7FFFh)
Bit Step: 0.5mA

7.6.31 REG0x2C_ADC_VSYS Register (Address = 2Ch) [Reset = 0000h]

REG0x2C_ADC_VSYS is shown in Figure 7-52 and described in Table 7-42.

Return to the Summary Table.

I2C REG0x2D=[15:8], I2C REG0x2C=[7:0]

Figure 7-52 REG0x2C_ADC_VSYS Register
15141312111098
ADC_VSYS
R-0h
76543210
ADC_VSYS
R-0h
Table 7-42 REG0x2C_ADC_VSYS Register Field Descriptions
BitFieldTypeResetNotesDescription
15-0ADC_VSYSR0hReset by:
REG_RESET		 VSYS ADC reading: POR: 0mV (0h)
Format: 2s Complement
Range: 0mV-65534mV (0h-7FFFh)
Clamped Low
Bit Step: 2mV

7.6.32 REG0x2E_Manufacture_ID Register (Address = 2Eh) [Reset = 40h]

REG0x2E_Manufacture_ID is shown in Figure 7-53 and described in Table 7-43.

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Figure 7-53 REG0x2E_Manufacture_ID Register
76543210
MANUFACTURE_ID
R-40h
Table 7-43 REG0x2E_Manufacture_ID Register Field Descriptions
BitFieldTypeResetNotesDescription
7-0MANUFACTURE_IDR40h Manufacture ID : 40h

7.6.33 REG0x2F_Device_ID Register (Address = 2Fh) [Reset = 09h]

REG0x2F_Device_ID is shown in Figure 7-54 and described in Table 7-44.

Return to the Summary Table.

Figure 7-54 REG0x2F_Device_ID Register
76543210
DEVICE_ID
R-9h
Table 7-44 REG0x2F_Device_ID Register Field Descriptions
BitFieldTypeResetNotesDescription
7-0DEVICE_IDR9h Device ID
BQ25773: 00 001 001(09h)

7.6.34 REG0x30_ChargeOption1 Register (Address = 30h) [Reset = 01h]

REG0x30_ChargeOption1 is shown in Figure 7-55 and described in Table 7-45.

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Figure 7-55 REG0x30_ChargeOption1 Register
76543210
SYSOVP_MAXCMP_POLCMP_DEGFRC_CONV_OFFEN_PTMEN_SHIP_DCHGEN_SC_VBUSACP
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-1h
Table 7-45 REG0x30_ChargeOption1 Register Field Descriptions
BitFieldTypeResetNotesDescription
7SYSOVP_MAXR/W0hReset by:
REG_RESET		 Force SYSOVP protection threshold to 27V neglecting CELL_BATPRES pin configuration 0b = Disable
1b = Enable
6CMP_POLR/W0hReset by:
REG_RESET		 Independent Comparator output Polarity 0b = When CMPIN_TR is above internal threshold, CMPOUT is LOW (internal
hysteresis)
1b = When CMPIN_TR is below internal threshold, CMPOUT is LOW (external
hysteresis)
5-4CMP_DEGR/W0hReset by:
REG_RESET		 Independent comparator deglitch time, only applied to the falling edge of
CMPOUT (HIGH to LOW). 00b = 1us(Not in battery only low power mode)/ 40us(Battery only low power mode) 01b = 2.05ms~2.73ms
10b = 20.85ms~27.31ms
11b = 5.34s~6.99s
3FRC_CONV_OFFR/W0hReset by:
REG_RESET		 Force Power Path Off
When independent comparator triggers, charger turns off Q1 and Q4 (same as
disable converter) so that the system is disconnected from the input source. At
the same time, CHRG_OK signal goes to LOW to notify the system. It should be effective during forward mode with AC plugged in or battery only performance mode. Both FRC_CONV_OFF and CMP_EN should be 1b to enable this feature. No need for EN_LWPWR, EN_LWPWR_CMP to be high which are employed under battery only low power mode. 0b = Disable
1b = Enable
2EN_PTMR/W0hReset by:
REG_RESET		 PTM enable register bit, it will automatically reset to zero 0b = Disable
1b = Enable
1EN_SHIP_DCHGR/W0hReset by:
REG_RESET		 Discharge SRN for Shipping Mode
Used to discharge SRN pin capacitor voltage which is necessary for battery gauge device shipping mode. When this bit is 1, discharge SRN pin down in 340 ms with around 20mA current flowing through VSYS pin. When 340 ms is over, this bit is reset to 0 automatically. If this bit is written to 0b by host before 340ms expires, VSYS pin should stop discharging immediately. After SRN is discharged to 0V the discharge current will shut off automatically in order to get rid of any negative voltage on SRN pin. Note if after 340ms SRN voltage is still not low enough for battery gauge device entering ship mode, the host may need to write this bit to 1b again to start a new 340ms discharge cycle. 0b = Disable
1b = Enable
0EN_SC_VBUSACPR/W1hReset by:
REG_RESET		 SC_VBUSACP protection enable register bit 0b = Disable
1b = Enable

7.6.35 REG0x31_ChargeOption1 Register (Address = 31h) [Reset = 32h]

REG0x31_ChargeOption1 is shown in Figure 7-56 and described in Table 7-46.

Return to the Summary Table.

Figure 7-56 REG0x31_ChargeOption1 Register
76543210
EN_IBATEN_LWPWR_CMPPSYS_CONFIGRSNS_RACRSNS_RSRPSYS_RATIOEN_OTG_BIG_CAP
R/W-0hR/W-0hR/W-3hR/W-0hR/W-0hR/W-1hR/W-0h
Table 7-46 REG0x31_ChargeOption1 Register Field Descriptions
BitFieldTypeResetNotesDescription
7EN_IBATR/W0hReset by:
REG_RESET		 IBAT Enable
Enable the IBAT output buffer. In low power mode (EN_LWPWR=1b), IBAT
buffer is always disabled regardless of this bit value. 0b = Disable
1b = Enable
6EN_LWPWR_CMPR/W0hReset by:
REG_RESET		 Independent Comparator Enable
Enable independent comparator under battery only low power mode(EN_LWPWR=1b) 0b = Disable
1b = Enable
5-4PSYS_CONFIGR/W3hReset by:
REG_RESET		 PSYS Enable and Definition Register
Enable PSYS sensing circuit and output buffer (whole PSYS circuit). In low power mode (EN_LWPWR=1b), PSYS sensing and buffer are always disabled regardless of this bit value. 00b = PBUS+PBAT
01b = PBUS
10b = RESERVED
11b = OFF
3RSNS_RACR/W0hReset by:
REG_RESET		 Input sense resistor RAC.Not recommend change this value during IINDPM/IOTG regulation: Under adapter plugged in: make changes right after converter starts up with light loading and before charge is enabled.
With battery only : make changes before EN_OTG pin is pulled up. 0b = 10 mOhms
1b = 5 mOhms
2RSNS_RSRR/W0hReset by:
REG_RESET		 Charge sense resistor RSR. Not recommend change this value during ICHG/IPRECHG/BATFET_CLAMP1/BATFET_CLAMP2/BAT_SHORT regulation:
Under adapter plugged in: make changes right after converter starts up with light loading and before charge is enabled.
With battery only : make changes before EN_OTG pin is pulled up. 0b = 5 mOhms
1b = 2 mOhms
1PSYS_RATIOR/W1hReset by:
REG_RESET		 PSYS Gain
Ratio of PSYS output current vs total input and battery power. 0b = 0p25uAperW
1b = 1p00uAperW
0EN_OTG_BIG_CAPR/W0hReset by:
REG_RESET		 Enable OTG compensation for VBUS effective capacitance larger than
60uF 0b = Disable OTG large VBUS capacitance compensation(Recommended
for VBUS effective capacitance smaller than 60uF effective capacitance)
1b = Enable OTG large VBUS capacitance compensation(Recommended
for VBUS effective capacitance larger than 60uF effective capacitance)

7.6.36 REG0x32_ChargeOption2 Register (Address = 32h) [Reset = B7h]

REG0x32_ChargeOption2 is shown in Figure 7-57 and described in Table 7-47.

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Figure 7-57 REG0x32_ChargeOption2 Register
76543210
EN_EXTILIMEN_ICHG_IDCHGOCP_SW2_HIGH_RANGEOCP_SW1X_HIGH_RANGEEN_ACOCACOC_VTHEN_BATDOCBATDOC_VTH
R/W-1hR/W-0hR/W-1hR/W-1hR/W-0hR/W-1hR/W-1hR/W-1h
Table 7-47 REG0x32_ChargeOption2 Register Field Descriptions
BitFieldTypeResetNotesDescription
7EN_EXTILIMR/W1hReset by:
REG_RESET		 Enable ILIM_HIZ pin to set input current limit 0b = Disable(Input current limit is set by IIN_HOST())
1b = Enable(Input current limit is set by the lower value of ILIM_HIZ pin and IIN_HOST())
6EN_ICHG_IDCHGR/W0hReset by:
REG_RESET		 IBAT pin monitor selection for discharge current and charge current 0b = IBAT pin as Discharge Current
1b = IBAT pin as Charge Current
5OCP_SW2_HIGH_RANGER/W1hReset by:
REG_RESET		 Over current protection threshold by sensing Q4 Vds. When this fault is continuously triggered 1 switching cycle, converter will be latched off. To re-enable converter, need to toggle EN_HIZ bit from 0 to 1 and back to 0. 0b = 150mV
1b = 260mV
4OCP_SW1X_HIGH_RANGER/W1hReset by:
REG_RESET		 Over current protection threshold by sensing RAC resistor across voltage, When this fault is continuously triggered 1 switching cycle, converter will be latched off. To re-enable converter, need to toggle EN_HIZ bit from 0 to 1 and back to 0. 0b = 300 mV (150mV under VSYS_UVP) for Q1_A and Q1_B
1b = 450 mV (300mV under VSYS_UVP) for Q1_A and Q1_B
3EN_ACOCR/W0hReset by:
REG_RESET		 ACOC Enable
Input overcurrent (ACOC) protection by sensing the voltage across ACP_A and ACN_A plus ACP_B and ACN_B. Upon ACOC (after 250-µs blank-out time), converter is disabled. 0b = Disable
1b = Enable
2ACOC_VTHR/W1hReset by:
REG_RESET		 ACOC Limit
Set ACOC threshold as percentage of ILIM2_VTH with current sensed from RAC. 0b = 1.33
1b = 2
1EN_BATDOCR/W1hReset by:
REG_RESET		 BATDOC Enable
Battery discharge overcurrent (BATDOC) protection by sensing the voltage across SRN and SRP. Upon BATDOC, converter is disabled. 0b = Disable
1b = Enable
0BATDOC_VTHR/W1hReset by:
REG_RESET		 Set battery discharge overcurrent threshold as percentage of
PROCHOT battery discharge current limit. 0b = 2
1b = 3

7.6.37 REG0x33_ChargeOption2 Register (Address = 33h) [Reset = 00h]

REG0x33_ChargeOption2 is shown in Figure 7-58 and described in Table 7-48.

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Figure 7-58 REG0x33_ChargeOption2 Register
76543210
PKPWR_TOVLD_DEGEN_PKPWR_IIN_DPMEN_PKPWR_VSYSSTAT_PKPWR_OVLDSTAT_PKPWR_RELAXPKPWR_TMAX
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-48 REG0x33_ChargeOption2 Register Field Descriptions
BitFieldTypeResetNotesDescription
7-6PKPWR_TOVLD_DEGR/W0hReset by:
REG_RESET		 Input Overload time in Peak Power Mode 00b = 1ms
01b = 2ms
10b = 5ms
11b = 10ms
5EN_PKPWR_IIN_DPMR/W0hReset by:
REG_RESET		 Enable Peak Power Mode triggered by input current overshoot. If EN_PKPWR_IIN_DPM and EN_PKPWR_VSYS are 0b, peak power mode is disabled. Upon adapter removal, this bits is reset to 0b. 0b = Disable
1b = Enable
4EN_PKPWR_VSYSR/W0hReset by:
REG_RESET		 Enable Peak Power Mode triggered by system voltage under-shoot. If EN_PKPWR_IIN_DPM and EN_PKPWR_VSYS are 0b, peak power mode is disabled. Upon adapter removal, this bits is reset to 0b. 0b = Disable
1b = Enable
3STAT_PKPWR_OVLDR/W0hReset by:
REG_RESET		 Indicator that the device is in overloading cycle. Write 0 to get out of
overloading cycle. 0b = Not In Peak
1b = In Peak
2STAT_PKPWR_RELAXR/W0hReset by:
REG_RESET		 Indicator that the device is in relaxation cycle. Write 0 to get out of relaxation cycle. 0b = Not In Relaxation
1b = In Relaxation
1-0PKPWR_TMAXR/W0hReset by:
REG_RESET		 Peak power mode overload and relax cycle time. 00b = 20ms
01b = 40ms
10b = 80ms
11b = 1s

7.6.38 REG0x34_ChargeOption3 Register (Address = 34h) [Reset = 34h]

REG0x34_ChargeOption3 is shown in Figure 7-59 and described in Table 7-49.

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Figure 7-59 REG0x34_ChargeOption3 Register
76543210
BATFET_ENZRESERVEDOTG_VAP_MODEIL_AVGCMP_ENBATFETOFF_HIZPSYS_OTG_IDCHG
R/W-0hR-0hR/W-1hR/W-2hR/W-1hR/W-0hR/W-0h
Table 7-49 REG0x34_ChargeOption3 Register Field Descriptions
BitFieldTypeResetNotesDescription
7BATFET_ENZR/W0hReset by:
REG_RESET		 Turn off BATFET under battery only low power mode. When not in low power mode like OTG or with AC plugged in, the bit configuration is neglected and not effective. 0b = Not force turn off BATFET
1b = Force turn off BATFET
6RESERVEDR0h Reserved
5OTG_VAP_MODER/W1hReset by:
REG_RESET		 The selection of the external EN_OTG pin control. 0b = VAP Mode
1b = OTG Mode
4-3IL_AVGR/W2hReset by:
REG_RESET		 4 levels inductor average current clamp. 00b = 10A
01b = 18A
10b = 24A
11b = Disable(internal 30A limit)
2CMP_ENR/W1hReset by:
REG_RESET		 Enable Independent Comparator with effective low. 0b = Disable
1b = Enable
1BATFETOFF_HIZR/W0hReset by:
REG_RESET		 Turn off BATFET during HIZ mode. 0b = On
1b = Off
0PSYS_OTG_IDCHGR/W0hReset by:
REG_RESET		 PSYS definition during OTG mode. 0b = PSYS as battery discharge power minus OTG output power
1b = PSYS as battery discharge power only

7.6.39 REG0x35_ChargeOption3 Register (Address = 35h) [Reset = 05h]

REG0x35_ChargeOption3 is shown in Figure 7-60 and described in Table 7-50.

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Figure 7-60 REG0x35_ChargeOption3 Register
76543210
EN_HIZREG_RESETDETECT_VINDPMEN_OTGEN_ICO_MODEEN_PORT_CTRLEN_VSYS_MIN_SOFT_SR
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-1hR/W-1h
Table 7-50 REG0x35_ChargeOption3 Register Field Descriptions
BitFieldTypeResetNotesDescription
7EN_HIZR/W0hReset by:
REG_RESET		 Device Hi-Z Mode Enable
When the charger is in Hi-Z mode, the device draws minimal quiescent current. With VBUS above UVLO. REGN LDO stays on, and system powers from battery. 0b = Disable
1b = Enable
6REG_RESETR/W0hReset by:
REG_RESET		 Reset Registers
All the R/W and R registers go back to the default setting except: CHRG_STAT, MODE_STAT, HIDRV1_STAT, LODRV1_STAT, HIDRV2_STAT, LODRV2_STAT, PWM_FREQ 0b = Idle
1b = Reset
5DETECT_VINDPMR/W0hReset by:
REG_RESET		 Set VINDPM threshold based on VBUS measurement result minus 1.28V, Converter is disabled to measure VBUS. After VBUS measurement is done, VINDPM() is written with value VBUS-1.28V. Then this bit goes back to 0 and converter starts. 0b = Idle
1b = Measure VIN, write VIN-1.28V to VINDPM
4EN_OTGR/W0hReset by:
REG_RESET
WATCHDOG		 OTG Mode Enable
Enable device in OTG mode when EN_OTG pin is HIGH. 0b = Disable
1b = Enable
3EN_ICO_MODER/W0hReset by:
REG_RESET		 Enable ICO Algorithm 0b = Disable
1b = Enable
2EN_PORT_CTRLR/W1hReset by:
REG_RESET		 Enable BATFET control for dual port application: 0b = Disable BATFET control by HIZ BATDRV pin
1b = Enable BATFET control by active BATDRV pin
1-0EN_VSYS_MIN_SOFT_SRR/W1hReset by:
REG_RESET		 VSYS_MIN soft slew rate control for VSYS_MIN step up transition. Note for step down doesn't need the soft transition. 00b = Disable
01b = 6.25mV/us
10b = 3.125mV/us
11b = 1.5625mV/us

7.6.40 REG0x36_ProchotOption0_Register (Address = 36h) [Reset = 39h]

REG0x36_ProchotOption0_Register is shown in Figure 7-61 and described in Table 7-51.

Return to the Summary Table.

Figure 7-61 REG0x36_ProchotOption0_Register
76543210
VSYS_TH1INOM_DEGLOWER_PROCHOT_VINDPM
R/W-EhR/W-0hR/W-1h
Table 7-51 REG0x36_ProchotOption0_Register Field Descriptions
BitFieldTypeResetNotesDescription
7-2VSYS_TH1R/WEhReset by:
REG_RESET		 VSYS threshold to trigger discharging VBUS in VAP mode. POR: 6400mV (Eh)
Range: 5000mV-11300mV (0h-3Fh)
Bit Step: 100mV
Offset: 5000mV
1INOM_DEGR/W0hReset by:
REG_RESET		 INOM deglitch time 0b = 0.84ms (min)/0.988ms (typ.)/1.14ms (max)
1b = 54ms (min)/64ms (typ.)/73ms (max)
0LOWER_PROCHOT_VINDPMR/W1hReset by:
REG_RESET		 Enable lower threshold of PROCHOT_VINDPM comparator: 0b = PROCHOT_VINDPM follows VINDPM REG0x3D setting
1b = PROCHOT_VINDPM is lowered and determined by PROCHOT_VINDPM_80_90 bit setting

7.6.41 REG0x37_ProchotOption0_Register (Address = 37h) [Reset = 4Ah]

REG0x37_ProchotOption0_Register is shown in Figure 7-62 and described in Table 7-52.

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Figure 7-62 REG0x37_ProchotOption0_Register
76543210
ILIM2_VTHICRIT_DEGPROCHOT_VINDPM_80_90
R/W-9hR/W-1hR/W-0h
Table 7-52 REG0x37_ProchotOption0_Register Field Descriptions
BitFieldTypeResetNotesDescription
7-3ILIM2_VTHR/W9hAdd notes here to describe
Reset by:
REG_RESET		 ILIM2 Threshold 00000b = OutOfRange_0x00
00001b = 110_percent
00010b = 115_percent
00011b = 120_percent
00100b = 125_percent
00101b = 130_percent
00110b = 135_percent
00111b = 140_percent
01000b = 145_percent
01001b = 150_percent
01010b = 155_percent
01011b = 160_percent
01100b = 165_percent
01101b = 170_percent
01110b = 175_percent
01111b = 180_percent
10000b = 185_percent
10001b = 190_percent
10010b = 195_percent
10011b = 200_percent
10100b = 205_percent
10101b = 210_percent
10110b = 215_percent
10111b = 220_percent
11000b = 225_percent
11001b = 230_percent
11010b = 250_percent
11011b = 300_percent
11100b = 350_percent
11101b = 400_percent
11110b = 450_percent
11111b = OutOfRange_0x1F
2-1ICRIT_DEGR/W1hReset by:
REG_RESET		 ICRIT deglitch time to trigger PROCHOT 00b = 12us(Min)/14.5us(Typ.)/17us(Max)
01b = 93us(Min)/111us(Typ.)/129us(Max)
10b = 372us(Min)/443us(Typ.)/513us(Max)
11b = 745us(Min)/873us(Typ.)/1000us(Max)
0PROCHOT_VINDPM_80_90R/W0hReset by:
REG_RESET		 Lower threshold of the PROCHOT_VINDPM comparator.
When LOWER_PROCHOT_VINDPM=1, the threshold of PROCHOT_VINDPM is determined by this setting. 0b = 83% of VINDPM
1b = 91% of VINDPM

7.6.42 REG0x38_ProchotOption1 Register (Address = 38h) [Reset = A0h]

REG0x38_ProchotOption1 is shown in Figure 7-63 and described in Table 7-53.

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Figure 7-63 REG0x38_ProchotOption1 Register
76543210
PP_VINDPMPP_CMPPP_ICRITPP_INOMPP_IDCHG1PP_VSYSPP_BATPRESPP_ACOK
R/W-1hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-53 REG0x38_ProchotOption1 Register Field Descriptions
BitFieldTypeResetNotesDescription
7PP_VINDPMR/W1hReset by:
REG_RESET		 VINDPM PROCHOT profile enable 0b = Disable
1b = Enable
6PP_CMPR/W0hReset by:
REG_RESET		 COMP PROCHOT profile enable 0b = Disable
1b = Enable
5PP_ICRITR/W1hReset by:
REG_RESET		 ICRIT PROCHOT profile enable 0b = Disable
1b = Enable
4PP_INOMR/W0hReset by:
REG_RESET		 INOM PROCHOT profile enable 0b = Disable
1b = Enable
3PP_IDCHG1R/W0hReset by:
REG_RESET		 IDCHG1 PROCHOT profile enable 0b = Disable
1b = Enable
2PP_VSYSR/W0hReset by:
REG_RESET		 VSYS PROCHOT profile enable 0b = Disable
1b = Enable
1PP_BATPRESR/W0hReset by:
REG_RESET		 Battery removal PROCHOT profile enable
If PP_BATPRES is enabled in PROCHOT after the battery is removed, it will immediately send out one-shot PROCHOT pulse. 0b = Disable
1b = Enable
0PP_ACOKR/W0hReset by:
REG_RESET		 Adapter removal PROCHOT profile enable.
If PP_ACOK is enabled in PROCHOT after the adapter is removed, it will be pulled low. 0b = Disable
1b = Enable

7.6.43 REG0x39_ProchotOption1 Register (Address = 39h) [Reset = 41h]

REG0x39_ProchotOption1 is shown in Figure 7-64 and described in Table 7-54.

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Figure 7-64 REG0x39_ProchotOption1 Register
76543210
IDCHG_TH1IDCHG_DEG1
R/W-10hR/W-1h
Table 7-54 REG0x39_ProchotOption1 Register Field Descriptions
BitFieldTypeResetNotesDescription
7-2IDCHG_TH1R/W10hReset by:
REG_RESET		 IDCHG level 1 Threshold
6 bit, range, range 1500A to 33A(5mΩ RSR), step 500 mA. There is a 1500 mA offset for all code
Measure current between SRN and SRP.
Trigger when the discharge current is above the threshold.
If the value is programmed to 000000b PROCHOT is always triggered.
Default: 9500 mA or 010000b POR: 9500mA (10h)
Range: 1500mA-33000mA (0h-3Fh)
Bit Step: 500mA
Offset: 1500mA
1-0IDCHG_DEG1R/W1hReset by:
REG_RESET		 IDCHG Deglitch Time 00b = 69ms(min)/78ms(Typ.)/93.6ms(max)
01b = 1.1sec(min)/1.25sec(Typ.)/1.4sec(max)
10b = 4.4sec(min)/5sec(Typ.)/5.6sec(max)
11b = 17.5sec(min)/20sec(Typ.)/22.3sec(max)

7.6.44 REG0x3A_ADCOption Register (Address = 3Ah) [Reset = 00h]

REG0x3A_ADCOption is shown in Figure 7-65 and described in Table 7-55.

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Figure 7-65 REG0x3A_ADCOption Register
76543210
EN_ADC_CMPINEN_ADC_VBUSEN_ADC_PSYSEN_ADC_IINRESERVEDEN_ADC_IBATEN_ADC_VSYSEN_ADC_VBAT
R/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 7-55 REG0x3A_ADCOption Register Field Descriptions
BitFieldTypeResetNotesDescription
7EN_ADC_CMPINR/W0hReset by:
REG_RESET		 Enable CMPIN_TR pin Voltage ADC Channel 0b = Disable
1b = Enable
6EN_ADC_VBUSR/W0hReset by:
REG_RESET		 Enable VBUS pin Voltage ADC Channel 0b = Disable
1b = Enable
5EN_ADC_PSYSR/W0hReset by:
REG_RESET		 Enable PSYS pin Voltage ADC Channel 0b = Disable
1b = Enable
4EN_ADC_IINR/W0hReset by:
REG_RESET		 Enable IIN ADC Channel 0b = Disable
1b = Enable
3RESERVEDR0h Reserved
2EN_ADC_IBATR/W0hReset by:
REG_RESET		 Enable ICHG ADC Channel 0b = Disable
1b = Enable
1EN_ADC_VSYSR/W0hReset by:
REG_RESET		 Enable VSYS pin Voltage ADC Channel 0b = Disable
1b = Enable
0EN_ADC_VBATR/W0hReset by:
REG_RESET		 Enable SRN pin Voltage ADC Channel 0b = Disable
1b = Enable

7.6.45 REG0x3B_ADCOption Register (Address = 3Bh) [Reset = 90h]

REG0x3B_ADCOption is shown in Figure 7-66 and described in Table 7-56.

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Figure 7-66 REG0x3B_ADCOption Register
76543210
ADC_RATEADC_ENADC_SAMPLEADC_AVGADC_AVG_INITRESERVED
R/W-1hR/W-0hR/W-1hR/W-0hR/W-0hR-0h
Table 7-56 REG0x3B_ADCOption Register Field Descriptions
BitFieldTypeResetNotesDescription
7ADC_RATER/W1hReset by:
REG_RESET		 ADC conversion type selection
Typical conversion time is determined by resolution accuracy. 0b = Continuous update. Cycling set of conversion updates to ADC registers without break. The total period of whole set is determined by the ADC channel enabled count times conversion time for each channel determined by ADC_SAMPLE setting.
1b = One-shot update. Do one set of conversion updates to ADC registers
after ADC_START =1. The total period of whole set is determined by the ADC channel enabled count times conversion time for each channel determined by ADC_SAMPLE setting.
6ADC_ENR/W0hReset by:
REG_RESET
WATCHDOG		 ADC conversion enable command.
Under one-shot ADC configuration ADC_RATE=0b, After the one-shot update is complete, this bit
automatically resets to zero 0b = Idle
1b = Start
5-4ADC_SAMPLER/W1hReset by:
REG_RESET		 ADC sample resolution selection, each channel conversion time is also determined based on resolution. 00b = 15 bits effective resolution(24ms conversion time per channel)
01b = 14 bits effective resolution(12ms conversion time per channel)
10b = 13 bits effective resolution(6ms conversion time per channel)
11b = Reserved
3ADC_AVGR/W0hReset by:
REG_RESET		 ADC average control 0b = Single Value
1b = Running average
2ADC_AVG_INITR/W0hReset by:
REG_RESET		 ADC average initial value control 0b = Start average using existing register value
1b = Start average using new ADC conversion
1-0RESERVEDR0h Reserved

7.6.46 REG0x3C_ChargeOption4 Register (Address = 3Ch) [Reset = 48h]

REG0x3C_ChargeOption4 is shown in Figure 7-67 and described in Table 7-57.

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Figure 7-67 REG0x3C_ChargeOption4 Register
76543210
IDCHG_DEG2IDCHG_TH2PP_IDCHG2STAT_IDCHG2STAT_PTM
R/W-1hR/W-1hR/W-0hR-0hR-0h
Table 7-57 REG0x3C_ChargeOption4 Register Field Descriptions
BitFieldTypeResetNotesDescription
7-6IDCHG_DEG2R/W1hReset by:
REG_RESET		 Battery discharge current limit 2 deglitch time 00b = 81us(min)/98us(Typ.)/115us(max)
01b = 1.3ms(min)/1.55ms(Typ.)/1.8ms(max)
10b = 5.2ms(min)/6.25ms(Typ.)/7.3ms(max)
11b = 10.4ms(min)/12.5ms(Typ.)/14.6ms(max)
5-3IDCHG_TH2R/W1hReset by:
REG_RESET		 Battery discharge current limit2 based on percentage of IDCHG_TH1. Note IDCHG_TH2 setting higher than 40A should lose accuracy derating between target value and 40A. 000b = 125%*IDCHG_TH1
001b = 150%*IDCHG_TH1
010b = 175%*IDCHG_TH1
011b = 200%*IDCHG_TH1
100b = 250%*IDCHG_TH1
101b = 300%*IDCHG_TH1
110b = 350%*IDCHG_TH1
111b = 400%*IDCHG_TH1
2PP_IDCHG2R/W0hReset by:
REG_RESET		 Enable IDCHG_TH2 PROCHOT Profile 0b = Disable
1b = Enable
1STAT_IDCHG2R0hReset by:
REG_RESET		 The status is latched until a read from host. 0b = Not Triggered
1b = Triggered
0STAT_PTMR0hReset by:
REG_RESET		 PTM operation status bit monitor 0b = Not Active
1b = Active

7.6.47 REG0x3D_ChargeOption4 Register (Address = 3Dh) [Reset = 00h]

REG0x3D_ChargeOption4 is shown in Figure 7-68 and described in Table 7-58.

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Figure 7-68 REG0x3D_ChargeOption4 Register
76543210
VSYS_UVPEN_DITHERVSYS_UVP_NO_HICCUPPP_VBUS_VAPSTAT_VBUS_VAP
R/W-0hR/W-0hR/W-0hR/W-0hR-0h
Table 7-58 REG0x3D_ChargeOption4 Register Field Descriptions
BitFieldTypeResetNotesDescription
7-5VSYS_UVPR/W0hReset by:
REG_RESET		 VSYS Under Voltage Lock Out After UVP is triggered the charger enters
hiccup mode, and then the charger is latched off if the restart fails 7 times
in 90s The hiccup mode during the UVP can be disabled by setting
VSYS_UVP_NO_HICCUP=1b. 000b = 2.4V
001b = 3.2V
010b = 4.0V
011b = 4.8V
100b = 5.6V
101b = 6.4V
110b = 7.2V
111b = 8.0V
4-3EN_DITHERR/W0hReset by:
REG_RESET		 Frequency Dither configuration 00b = Disable
01b = 1X
10b = 2X
11b = 3X
2VSYS_UVP_NO_HICCUPR/W0hReset by:
REG_RESET		 Disable VSYS_UVP Hiccup mode operation: 0b = Hiccup Mode Enabled
1b = Hiccup Mode Disabled
1PP_VBUS_VAPR/W0hReset by:
REG_RESET		 Enable VBUS_VAP PROCHOT Profile 0b = Disable
1b = Enable
0STAT_VBUS_VAPR0hReset by:
REG_RESET		 STAT_VBUS_VAP 0b = Not Triggered
1b = Triggered

7.6.48 REG0x3E_Vmin_Active_Protection Register (Address = 3Eh) [Reset = 24h]

REG0x3E_Vmin_Active_Protection is shown in Figure 7-69 and described in Table 7-59.

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Figure 7-69 REG0x3E_Vmin_Active_Protection Register
76543210
VSYS_TH2EN_VSYSTH2_FOLLOW_VSYSTH1EN_FRS
R/W-9hR/W-0hR/W-0h
Table 7-59 REG0x3E_Vmin_Active_Protection Register Field Descriptions
BitFieldTypeResetNotesDescription
7-2VSYS_TH2R/W9hReset by:
REG_RESET		 VAP Mode2 VBUS /PROCHOT trigger voltage threshold POR: 5900mV (9h)
Range: 5000mV-11300mV (0h-3Fh)
Bit Step: 100mV
Offset: 5000mV
1EN_VSYSTH2_FOLLOW_VSYSTH1R/W0hReset by:
REG_RESET		 Enable internal VSYS_TH2 follow VSYS_TH1 setting neglecting register VSYS_TH2 setting 0b = Disable
1b = Enable
0EN_FRSR/W0hReset by:
REG_RESET		 Fast Role Swap Feature Enable 0b = Disable
1b = Enable

7.6.49 REG0x3F_Vmin_Active_Protection Register (Address = 3Fh) [Reset = 00h]

REG0x3F_Vmin_Active_Protection is shown in Figure 7-70 and described in Table 7-60.

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Figure 7-70 REG0x3F_Vmin_Active_Protection Register
76543210
VBUS_VAP_THDIS_BATOVP_20MA
R/W-0hR/W-0h
Table 7-60 REG0x3F_Vmin_Active_Protection Register Field Descriptions
BitFieldTypeResetNotesDescription
7-1VBUS_VAP_THR/W0hReset by:
REG_RESET		 VAP Mode2 VBUS /PROCHOT trigger voltage threshold POR: 3200mV (0h)
Range: 3200mV-15900mV (0h-7Fh)
Bit Step: 100mV
Offset: 3200mV
0DIS_BATOVP_20MAR/W0hReset by:
REG_RESET		 Disable BATOVP 20mA discharge current through VSYS pin 0b = Discharge 20mA under BATOVP
1b = Not discharge 20mA under BATOVP

7.6.50 REG0x60_AUTOTUNE_READ Register (Address = 60h) [Reset = 00h]

REG0x60_AUTOTUNE_READ is shown in Figure 7-71 and described in Table 7-61.

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Figure 7-71 REG0x60_AUTOTUNE_READ Register
76543210
AUTOTUNE_B
R-0h
Table 7-61 REG0x60_AUTOTUNE_READ Register Field Descriptions
BitFieldTypeResetNotesDescription
7-0AUTOTUNE_BR0h Phase B inductor time constant L(uH)/DCR(mΩ) value: AUTOTUNE_A= 256-265*L(uH)/DCR(mΩ). When converter shuts off these bits are set back to 0.

7.6.51 REG0x61_AUTOTUNE_READ Register (Address = 61h) [Reset = 00h]

REG0x61_AUTOTUNE_READ is shown in Figure 7-72 and described in Table 7-62.

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Figure 7-72 REG0x61_AUTOTUNE_READ Register
76543210
AUTOTUNE_A
R-0h
Table 7-62 REG0x61_AUTOTUNE_READ Register Field Descriptions
BitFieldTypeResetNotesDescription
7-0AUTOTUNE_AR0h Phase A inductor time constant L(uH)/DCR(mΩ) value: AUTOTUNE_A= 256-265*L(uH)/DCR(mΩ). When converter shuts off these bits are set back to 0.

7.6.52 REG0x62_AUTOTUNE_FORCE Register (Address = 62h) [Reset = C8h]

REG0x62_AUTOTUNE_FORCE is shown in Figure 7-73 and described in Table 7-63.

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Figure 7-73 REG0x62_AUTOTUNE_FORCE Register
76543210
FORCE_AUTOTUNE_B
R/W-C8h
Table 7-63 REG0x62_AUTOTUNE_FORCE Register Field Descriptions
BitFieldTypeResetNotesDescription
7-0FORCE_AUTOTUNE_BR/WC8h Force value for phase B inductor time constant L(uH)/DCR(mΩ): FORCE_AUTOTUNE_B= 256-265*L(uH)/DCR(mΩ) Default 0xC8 refers to 0.211 uH/mΩ

7.6.53 REG0x63_AUTOTUNE_FORCE Register (Address = 63h) [Reset = C8h]

REG0x63_AUTOTUNE_FORCE is shown in Figure 7-74 and described in Table 7-64.

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Figure 7-74 REG0x63_AUTOTUNE_FORCE Register
76543210
FORCE_AUTOTUNE_A
R/W-C8h
Table 7-64 REG0x63_AUTOTUNE_FORCE Register Field Descriptions
BitFieldTypeResetNotesDescription
7-0FORCE_AUTOTUNE_AR/WC8h Force value for phase A inductor time constant L(uH)/DCR(mΩ) : FORCE_AUTOTUNE_A= 256-265*L(uH)/DCR(mΩ). Default 0xC8 refers to 0.211 uH/mΩ

7.6.54 REG0x64_GM_ADJUST_FORCE Register (Address = 64h) [Reset = C7h]

REG0x64_GM_ADJUST_FORCE is shown in Figure 7-75 and described in Table 7-65.

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Figure 7-75 REG0x64_GM_ADJUST_FORCE Register
76543210
FORCE_GM_ADJUSTFORCE_GM_ADJUST_ENFORCE_AUTOTUNE_EN
R/W-31hR/W-1hR/W-1h
Table 7-65 REG0x64_GM_ADJUST_FORCE Register Field Descriptions
BitFieldTypeResetNotesDescription
7-2FORCE_GM_ADJUSTR/W31h Force GM adjustment value for inductor DCR: GM_ADJUST= 71.25-272/DCR(mΩ) Default value 0x31 refers to 12.2mΩ
1FORCE_GM_ADJUST_ENR/W1h Enable FORCE_GM_ADJUST effective for inductor DCR current sense. Converter will automatically shuts off and restart when FORCE_UPDATE bit is written from 0b to 1b to update these force values. When converter restarts from other reason, as long as this bit is 1b, converter will force GM_ADJUST = FORCE_GM_ADJUST+1 as fixed value 0b = Disable FORCE_GM_ADJUST
1b = Enable FORCE_GM_ADJUST
0FORCE_AUTOTUNE_ENR/W1h Enable FORCE_AUTOTUNE_A, FORCE_AUTOTUNE_B effective for inductor DCR current sense. Converter will automatically shuts off and restart when FORCE_UPDATE bit is written from 0b to 1b to update these force values. When converter restarts from other reasons, as long as this bit is 1b, converter will follow the FORCE_AUTO_TUNE_A/B value and there is no auto calibration at beginning anymore. 0b = Disable FORCE_AUTOTUNE_A,FORCE_AUTOTUNE_B
1b = Enable FORCE_AUTOTUNE_A,FORCE_AUTOTUNE_B

7.6.55 REG0x65_GM_ADJUST_FORCE Register (Address = 65h) [Reset = 00h]

REG0x65_GM_ADJUST_FORCE is shown in Figure 7-76 and described in Table 7-66.

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Figure 7-76 REG0x65_GM_ADJUST_FORCE Register
76543210
GM_ADJUSTFORCE_UPDATERESERVED
R-0hR/W-0hR-0h
Table 7-66 REG0x65_GM_ADJUST_FORCE Register Field Descriptions
BitFieldTypeResetNotesDescription
7-2GM_ADJUSTR0h Auto adaptive adjustment value for inductor DCR. This value is 0 when converter shuts off. If converter starts switching and FORCE_GM_ADJUST_EN=1b then GM_ADJUST=FORCE_GM_ADJUST+1 as fixed value.
1FORCE_UPDATER/W0h Update FORCE_AUTOTUNE_A, FORCE_AUTOTUNE_B, FORCE_GM_ADJUST value to be effective for inductor DCR current sense. Converter will automatically shuts off and restart when this bit is written from 0b to 1b to login new force values. After one time update completes, the converter automatically recovers switching and reset this bit to 0b. 0b = Idle
1b = Update FORCE_AUTOTUNE_A,FORCE_AUTOTUNE_B, FORCE_GM_ADJUST values to converter
0RESERVEDR0h Reserved

7.6.56 REG0x80_VIRTUAL_CONTROL Register (Address = 80h) [Reset = 13h]

REG0x80_VIRTUAL_CONTROL is shown in Figure 7-77 and described in Table 7-67.

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Figure 7-77 REG0x80_VIRTUAL_CONTROL Register
76543210
REG_RESETRESERVEDEN_EXTILIMRESERVEDWD_RSTWDTMR_ADJ
R/W-0hR-0hR/W-1hR-0hR/W-0hR/W-3h
Table 7-67 REG0x80_VIRTUAL_CONTROL Register Field Descriptions
BitFieldTypeResetNotesDescription
7REG_RESETR/W0hReset by:
REG_RESET		 Reset Registers
All the R/W and R registers go back to the default setting except: CHRG_STAT, MODE_STAT, HIDRV1_STAT, LODRV1_STAT, HIDRV2_STAT, LODRV2_STAT 0b = Idle
1b = Reset
6-5RESERVEDR0h Reserved
4EN_EXTILIMR/W1hReset by:
REG_RESET		 Enable ILIM_HIZ pin to set input current limit 0b = Disable(Input current limit is set by IIN_HOST())
1b = Enable(Input current limit is set by the lower value of ILIM_HIZ pin and IIN_HOST())
3RESERVEDR0h Reserved
2WD_RSTR/W0hReset by:
REG_RESET		 Reset watch dog timer control: 0b = Normal
1b = Reset(bit goes back to 0 after timer reset)
1-0WDTMR_ADJR/W3hReset by:
REG_RESET		 WATCHDOG Timer Adjust
Set maximum delay between consecutive EC host write of charge voltage or charge current command.
If device does not receive a write on the CHARGE_VOLTAGE() or the CHARGE_CURRENT() within the watchdog time period, the charger will be suspended by setting the CHARGE_CURRENT() to 0 mA. After expiration, the timer will resume upon the write of CHARGE_CURRENT(), CHARGE_VOLTAGE() ,WDTMR_ADJ or WD_RST=1b. The charger will resume if the values are valid. 00b = Disable
01b = 5 sec
10b = 88 sec
11b = 175 sec

7.6.57 REG0x81_VIRTUAL_CONTROL Register (Address = 81h) [Reset = 00h]

REG0x81_VIRTUAL_CONTROL is shown in Figure 7-78 and described in Table 7-68.

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Figure 7-78 REG0x81_VIRTUAL_CONTROL Register
76543210
EN_AUTO_CHGRESERVEDEN_OTG
R/W-0hR-0hR/W-0h
Table 7-68 REG0x81_VIRTUAL_CONTROL Register Field Descriptions
BitFieldTypeResetNotesDescription
7EN_AUTO_CHGR/W0hReset by:
REG_RESET		 Automatic charge control(recharge and terminate battery charging automatically): 0b = Disable
1b = Enable
6-1RESERVEDR0h Reserved
0EN_OTGR/W0hReset by:
REG_RESET
WATCHDOG		 OTG Mode Enable
Enable device in OTG mode when EN_OTG pin is HIGH. 0b = Disable
1b = Enable