SLUSEK7 September   2024 BQ25773

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics BQ2577X
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequence
      2. 7.3.2  MODE Pin Detection
      3. 7.3.3  REGN Regulator (REGN LDO)
      4. 7.3.4  Independent Comparator Function
      5. 7.3.5  Battery Charging Management
        1. 7.3.5.1 Autonomous Charging Cycle
        2. 7.3.5.2 Battery Charging Profile
        3. 7.3.5.3 Charging Termination
        4. 7.3.5.4 Charging Safety Timer
      6. 7.3.6  Temperature Regulation (TREG)
      7. 7.3.7  Vmin Active Protection (VAP) When Battery Only Mode
      8. 7.3.8  Two Level Battery Discharge Current Limit
      9. 7.3.9  Fast Role Swap Feature
      10. 7.3.10 CHRG_OK Indicator
      11. 7.3.11 Input and Charge Current Sensing
      12. 7.3.12 Input Current and Voltage Limit Setup
      13. 7.3.13 Battery Cell Configuration
      14. 7.3.14 Device HIZ State
      15. 7.3.15 USB On-The-Go (OTG)
      16. 7.3.16 Quasi Dual Phase Converter Operation
      17. 7.3.17 Continuous Conduction Mode (CCM)
      18. 7.3.18 Pulse Frequency Modulation (PFM)
      19. 7.3.19 Switching Frequency and Dithering Feature
      20. 7.3.20 Current and Power Monitor
        1. 7.3.20.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 7.3.20.2 High-Accuracy Power Sense Amplifier (PSYS)
      21. 7.3.21 Input Source Dynamic Power Management
      22. 7.3.22 Integrated 16-Bit ADC for Monitoring
      23. 7.3.23 Input Current Optimizer (ICO)
      24. 7.3.24 Two-Level Adapter Current Limit (Peak Power Mode)
      25. 7.3.25 Processor Hot Indication
        1. 7.3.25.1 PROCHOT During Low Power Mode
        2. 7.3.25.2 PROCHOT Status
      26. 7.3.26 Device Protection
        1. 7.3.26.1  Watchdog Timer (WD)
        2. 7.3.26.2  Input Overvoltage Protection (ACOV)
        3. 7.3.26.3  Input Overcurrent Protection (ACOC)
        4. 7.3.26.4  System Overvoltage Protection (SYSOVP)
        5. 7.3.26.5  Battery Overvoltage Protection (BATOVP)
        6. 7.3.26.6  Battery Charge Overcurrent Protection (BATCOC)
        7. 7.3.26.7  Battery Discharge Overcurrent Protection (BATDOC)
        8. 7.3.26.8  BATFET Charge Current Clamp Protection under LDO Regulation Mode
        9. 7.3.26.9  Sleep Comparator Protection Between VBUS and ACP_A (SC_VBUSACP)
        10. 7.3.26.10 High Duty Buck Exit Comparator Protection (HDBCP)
        11. 7.3.26.11 REGN Power Good Protection (REGN_PG)
        12. 7.3.26.12 System Under Voltage Lockout (VSYS_UVP) and Hiccup Mode
        13. 7.3.26.13 OTG Mode Over Voltage Protection (OTG_OVP)
        14. 7.3.26.14 OTG Mode Under Voltage Protection (OTG_UVP)
        15. 7.3.26.15 Thermal Shutdown (TSHUT)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forward Mode
        1. 7.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 7.4.1.2 Battery Charging
      2. 7.4.2 USB On-The-Go Mode
      3. 7.4.3 Pass Through Mode (PTM)-Patented Technology
      4. 7.4.4 Learn Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
        1. 7.5.1.1 Timing Diagrams
        2. 7.5.1.2 Data Validity
        3. 7.5.1.3 START and STOP Conditions
        4. 7.5.1.4 Byte Format
        5. 7.5.1.5 Acknowledge (ACK) and Not Acknowledge (NACK)
        6. 7.5.1.6 Target Address and Data Direction Bit
        7. 7.5.1.7 Single Read and Write
        8. 7.5.1.8 Multi-Read and Multi-Write
        9. 7.5.1.9 Write 2-Byte I2C Commands
    6. 7.6 BQ25773 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Snubber and Filter for Voltage Spike Damping
        2. 8.2.2.2 ACP-ACN Input Filter
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Power MOSFETs Selection
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Layout Example Reference Top View
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • REE|36
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

BQ25773 BQ2577336-Pin WQFNTop View Figure 5-1 BQ2577336-Pin WQFNTop View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NUMBER
LODRV1_A 1 AO Buck phase A low side power MOSFET (Q2_A) driver. Connect to low side N-channel MOSFET gate.
REGN_A 2 PWR 5-V linear regulator output supplied from VBUS or VSYS. The LDO is active when VBUS above VVBUS_CONVEN. Connect a 2.2- or 3.3-μF ceramic capacitor from REGN_A to power ground. REGN_A pin output is for power stage gate drive and pull up voltage source.
BTST1_A 3 PWR Buck phase A high side power MOSFET driver power supply. Connect a 0.1-µF capacitor between SW1_A and BTST1_A. The bootstrap diode between REGN_A and BTST1_A is integrated.
HIDRV1_A 4 AO Buck phase A high side power MOSFET (Q1_A) driver. Connect to high side N-channel MOSFET gate.
SW1_A 5 PWR Buck phase A switching node. Connect to the source of the phase A buck half bridge high side n-channel MOSFET.
VBUS 6 PWR Charger input voltage. An input low-pass filter of 1 Ω and 0.47 µF (minimum) is recommended.
ACN_B 7 PWR Phase B input current sense amplifier negative input. A RC low-pass filter is required to be placed between the sense resistor and the ACN_B pin to suppress the high frequency noise in the input current signal. Refer to Section 8.2.2.2 for filter design.
ACP_B 8 PWR Phase B input current sense amplifier positive input. A RC low-pass filter is required to be placed between the sense resistor and the ACP_B pin to suppress the high frequency noise in the input current signal. Refer to Section 8.2.2.2 for filter design.
ACN_A 9 PWR Phase A input current sense amplifier negative input. A RC low-pass filter is required to be placed between the sense resistor and the ACN_A pin to suppress the high frequency noise in the input current signal. Refer to Section 8.2.2.2 for filter design.
ACP_A 10 PWR Phase A input current sense amplifier positive input. A RC low-pass filter is required to be placed between the sense resistor and the ACP_A pin to suppress the high frequency noise in the input current signal. Refer to Section 8.2.2.2 for filter design.
CHRG_OK 11 DO Open drain active high indicator to inform the system good power source is connected to the charger input. Connect to the pullup rail via a 10-kΩ resistor. When VBUS rises above 3.5 V and falls below VACOV_FALL, CHRG_OK is HIGH after 50-ms deglitch time. When VBUS falls below 3.2 V or rises above VACOV_RISE, CHRG_OK is LOW. When specific faults occur, CHRG_OK is asserted LOW. The pin can also be configured as interrupt source when CHRG_STAT changes with user register CHRG_OK_INT=1b.
EN_OTG 12 DI Active HIGH to enable OTG, VAP or FRS modes. 1) When OTG_VAP_MODE=1b and EN_OTG=1b, pulling high this pin can enable OTG mode. 2) When OTG_VAP_MODE=1b and EN_FRS=1b, pulling high this pin can enable FRS mode in forward operation. 3) When OTG_VAP_MODE=0b, pulling high EN_OTG pin to enable VAP mode. Refer to Table 7-5for details.
ILIM_HIZ 13 AI Input current limit setting pin. Program ILIM_HIZ voltage by connecting a resistor divider from REGN_A rail to ground. The pin voltage is calculated as: V(ILIM_HIZ) = 1 V + 40 × IINDPM × Rac, in which IIN_DPM is the target input current limit.
When the pin voltage is above VILIM_ENZ threshold, the external current limit function is disabled neglecting EN_EXTILIM bit status. When the pin voltage drops below VILIM_EN threshold, then external current limit will follow EN_EXTILIM bit status. If EN_EXTILIM = 1b the input current limit used by the charger is the lower setting of ILIM_HIZ pin and IIN_HOST register. If EN_EXTILIM = 0b input current limit is only determined by IIN_HOST register.
When the pin voltage is below 0.4 V, the device enters high impedance (HIZ) mode with low quiescent current. When the pin voltage is above 0.8 V, the device is out of HIZ mode. The ILIM_HIZ pin voltage is continuous read and used for updating current limit setting (If EN_EXTILIM=1b ), this allows dynamic change input current limit setting by adjusting this pin voltage.
IADPT 14 AO The adapter current monitoring output pin. VIADPT = 20 or 40 × (VACP_B – VACN_B+VACP_A – VACN_A) with ratio selectable through IADPT_GAIN bit. Place a 100-pF or less ceramic decoupling capacitor from IADPT pin to ground. This pin can be floating if not in use. IADPT output voltage is clamped below 3.2 V.
IBAT 15 AO The battery current monitoring output pin. VIBAT = 8 or 64 × (VSRP – VSRN) for charge current, or VIBAT = 8 or 64 × (VSRN – VSRP) for discharge current, with ratio selectable through IBAT_GAIN bit. Place a 100-pF or less ceramic decoupling capacitor from IBAT pin to ground. This pin can be floating if not in use. Its output voltage is clamped below 3.2 V.
MODE 16 AI Charger operation mode pin. Pull down resistor is needed on this MODE pin referring to Table 7-1.
PSYS 17 AO Current mode system power monitor. The output current is proportional to the total power from the adapter and the battery. The gain is selectable through host communication interface. Place a resistor from PSYS to ground to generate output voltage. This pin can be floating if not in use. Its output voltage is clamped at 3.2 V. Place a capacitor in parallel with the resistor for filtering.
PROCHOT 18 DO Active low open drain output indicator. It monitors adapter input current, battery discharge current, and system voltage. After any event in the PROCHOT profile is triggered, a pulse is asserted. The minimum pulse width is adjustable through PROCHOT_WIDTH bits.
SDA 19 DI/O I2C open-drain data I/O. Connect to data line from the host controller or smart battery. Connect a 10-kΩ pullup resistor according to I2C specifications. When communication frequency is increased to 1 Mhz, the pullup resistance may need to be reduced accordingly based on line capacitance.
SCL 20 DI I2C clock input. Connect to clock line from the host controller or smart battery. Connect a 10-kΩ pullup resistor according to specifications. When communication frequency is increased to 1 Mhz, the pullup resistance may need to be reduced accordingly based on line capacitance.
CMPOUT 21 DO Open-drain output of independent comparator. Place a pullup resistor from CMPOUT to pullup supply rail. Comparator polarity and deglitch time are selectable through user register.
CMPIN_TR 22 AI Input of independent comparator, the independent comparator compares the voltage sensed on CMPIN_TR pin with internal reference, and its output is on CMPOUT pin. Comparator polarity and deglitch time is selectable by the host. With polarity HIGH (CMP_POL = 1b), place a resistor between CMPIN_TR and CMPOUT to program hysteresis. With polarity LOW (CMP_POL = 0b), the internal hysteresis is 100 mV. If the independent comparator is not in use, tie CMPIN_TR to ground. When CMPIN_TR_SELECT=1b , it is the temperature feedback pin for an internally compensated temperature regulation loop.
CELL_BATPRES 23 AI Battery cell selection pin for 2–5-cell battery setting. CELL_BATPRES pin should be biased from REGN_A through a resistor divider (40% for 2s, 55% for 3s ,75% for 4s and 100% for 5s). CELL_BATPRES pin also sets SYSOVP thresholds to 12 V for 2-cell, 17 V for 3-cell, 22 V for 4-cell and 27 V for 5-cell. CELL_BATPRES pin is pulled below VCELL_BATPRES_FALL to indicate battery removal. No external cap is allowed at CELL_BATPRES pin. The total pull down impedance externally from CELL_BATPRES pin to GND should be no larger than 1 MΩ.
SRN 24 PWR Charge current sense amplifier negative input. SRN pin is for battery voltage sensing as well. Connect a 0.1-μF filter cap cross battery charging sensing resistor and use 10-Ω contact resistor between SRN pin and battery charging sensing resistor.
SRP 25 PWR Charge current sense amplifier positive input. Connect a 0.1-μF filter cap cross battery charging sensing resistor and use 10-Ω contact resistor between SRP pin and battery charging sensing resistor.
BATDRV 26 AO N-channel battery FET (BATFET) gate driver output. It is shorted to SRP to turn off the BATFET. It goes 5 V above SRP to fully turn on BATFET. BATFET is in linear mode to regulate VSYS at VSYS_MIN() when battery is depleted below VSYS_MIN() setting. BATFET is fully on during fast charge and works as an ideal-diode in supplement mode.
VSYS 27 PWR Charger system voltage sensing pin.
SW2 28 PWR Boost side switching node. Connect to the source of the boost half bridge high side N-channel MOSFET.
HIDRV2 29 AO Boost high side power MOSFET(Q4) driver. Connect to high side N-channel MOSFET gate.
BTST2 30 PWR Boost high side power MOSFET driver power supply. Connect a 0.1-μF capacitor between SW2 and BTST2. The bootstrap diode between REGN_B and BTST2 is integrated.
LODRV2 31 AO Boost low side power MOSFET (Q3) driver. Connect to low side N-channel MOSFET gate.
REGN_B 32 PWR 5-V linear regulator output supplied from VBUS or VSYS. The LDO is active when VBUS above VVBUS_CONVEN. Connect a 2.2- or 3.3-μF ceramic capacitor from REGN_B to power ground. REGN_B pin output is for power stage gate drive. Internally connected to REGN_A.
LODRV1_B 33 AO Buck phase B low side power MOSFET (Q2_B) driver. Connect to low side N-channel MOSFET gate.
BTST1_B 34 PWR Buck phase B high side power MOSFET driver power supply. Connect a 0.1-µF capacitor between SW1_B and BTST1_B. The bootstrap diode between REGN_B and BTST1_B is integrated.
HIDRV1_B 35 AO Buck phase B high side power MOSFET (Q1_B) driver. Connect to high side N-channel MOSFET gate.
SW1_B 36 PWR Buck side phase B switching node. Connect to the source of the phase B buck half bridge high side N-channel MOSFET.
Bottom pad (PGND) – PWR Exposed pad beneath the IC as common PGND. Unless otherwise stated, signals are referenced to the PGND pin. Use the bottom pads as the thermal pad for heat dissipation. Have multiple vias on the thermal pad plane connecting to power ground planes.