SLUSEK7 September   2024 BQ25773

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics BQ2577X
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequence
      2. 7.3.2  MODE Pin Detection
      3. 7.3.3  REGN Regulator (REGN LDO)
      4. 7.3.4  Independent Comparator Function
      5. 7.3.5  Battery Charging Management
        1. 7.3.5.1 Autonomous Charging Cycle
        2. 7.3.5.2 Battery Charging Profile
        3. 7.3.5.3 Charging Termination
        4. 7.3.5.4 Charging Safety Timer
      6. 7.3.6  Temperature Regulation (TREG)
      7. 7.3.7  Vmin Active Protection (VAP) When Battery Only Mode
      8. 7.3.8  Two Level Battery Discharge Current Limit
      9. 7.3.9  Fast Role Swap Feature
      10. 7.3.10 CHRG_OK Indicator
      11. 7.3.11 Input and Charge Current Sensing
      12. 7.3.12 Input Current and Voltage Limit Setup
      13. 7.3.13 Battery Cell Configuration
      14. 7.3.14 Device HIZ State
      15. 7.3.15 USB On-The-Go (OTG)
      16. 7.3.16 Quasi Dual Phase Converter Operation
      17. 7.3.17 Continuous Conduction Mode (CCM)
      18. 7.3.18 Pulse Frequency Modulation (PFM)
      19. 7.3.19 Switching Frequency and Dithering Feature
      20. 7.3.20 Current and Power Monitor
        1. 7.3.20.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 7.3.20.2 High-Accuracy Power Sense Amplifier (PSYS)
      21. 7.3.21 Input Source Dynamic Power Management
      22. 7.3.22 Integrated 16-Bit ADC for Monitoring
      23. 7.3.23 Input Current Optimizer (ICO)
      24. 7.3.24 Two-Level Adapter Current Limit (Peak Power Mode)
      25. 7.3.25 Processor Hot Indication
        1. 7.3.25.1 PROCHOT During Low Power Mode
        2. 7.3.25.2 PROCHOT Status
      26. 7.3.26 Device Protection
        1. 7.3.26.1  Watchdog Timer (WD)
        2. 7.3.26.2  Input Overvoltage Protection (ACOV)
        3. 7.3.26.3  Input Overcurrent Protection (ACOC)
        4. 7.3.26.4  System Overvoltage Protection (SYSOVP)
        5. 7.3.26.5  Battery Overvoltage Protection (BATOVP)
        6. 7.3.26.6  Battery Charge Overcurrent Protection (BATCOC)
        7. 7.3.26.7  Battery Discharge Overcurrent Protection (BATDOC)
        8. 7.3.26.8  BATFET Charge Current Clamp Protection under LDO Regulation Mode
        9. 7.3.26.9  Sleep Comparator Protection Between VBUS and ACP_A (SC_VBUSACP)
        10. 7.3.26.10 High Duty Buck Exit Comparator Protection (HDBCP)
        11. 7.3.26.11 REGN Power Good Protection (REGN_PG)
        12. 7.3.26.12 System Under Voltage Lockout (VSYS_UVP) and Hiccup Mode
        13. 7.3.26.13 OTG Mode Over Voltage Protection (OTG_OVP)
        14. 7.3.26.14 OTG Mode Under Voltage Protection (OTG_UVP)
        15. 7.3.26.15 Thermal Shutdown (TSHUT)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forward Mode
        1. 7.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 7.4.1.2 Battery Charging
      2. 7.4.2 USB On-The-Go Mode
      3. 7.4.3 Pass Through Mode (PTM)-Patented Technology
      4. 7.4.4 Learn Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
        1. 7.5.1.1 Timing Diagrams
        2. 7.5.1.2 Data Validity
        3. 7.5.1.3 START and STOP Conditions
        4. 7.5.1.4 Byte Format
        5. 7.5.1.5 Acknowledge (ACK) and Not Acknowledge (NACK)
        6. 7.5.1.6 Target Address and Data Direction Bit
        7. 7.5.1.7 Single Read and Write
        8. 7.5.1.8 Multi-Read and Multi-Write
        9. 7.5.1.9 Write 2-Byte I2C Commands
    6. 7.6 BQ25773 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Snubber and Filter for Voltage Spike Damping
        2. 8.2.2.2 ACP-ACN Input Filter
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Power MOSFETs Selection
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Layout Example Reference Top View
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • REE|36
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.6 Temperature Regulation (TREG)

In high power application, monitoring and controlling external component temperature can enhance reliability by limiting the total converter power under certain scenarios. The CMPIN_TR pin can be configured as temperature regulation feedback sensing pin when CMPIN_TR_SELECT=1b. It is the temperature feedback pin temperature regulation loop. The external voltage divider circuit is shown in Figure 7-5 consisting of RS and NTC resistor RTH. External NTC is placed where temperature is regulated (for example charger power stage) and generates feedback voltage on CMPIN_TR pin based on temperature variation. When temperature is lower than target, the voltage should be above 1.2 V, temperature regulation is not effective and TREG_STAT=0b ; As temperature increases, CMPIN_TR pin voltage drops to VTREG=1.2 V or lower , converter begin to reduce converter current and regulate CMPIN_TR voltage to stay at 1.2 V and set TREG_STAT=1b which is locked until host read or REG_RESET bit action.

To enable temperature regulation feature:

  • Set CMPIN_TR_SELECT=1b to configure CMPIN_TR_SELECT pin as temperature regulation feedback pin.
  • Make sure AC is plugged in and charge is enabled CHARGE_CURRENT() is non-zero and CHRG_INHIBIT=0b).
  • Set EN_TREG=1b to enable temperature regulation and pull CMPOUT pin to GND.

The RS and NTC resistor RTH network generate some quiescent current which may not be negligible under light load. In order to reduce quiescent current under light load, instead of pull down RTH to GND locally at power stage, we can pull down through CMPOUT pin shown in Figure 7-5. Under either TREG is enabled (CMPIN_TR_SELECT=1b & EN_TREG=1b) or thermal PROCHOT channel is enabled (CMPIN_TR_SELECT=1b & PP_THERMAL=1b), then CMPOUT pin is pulled down to GND to generate sensing voltage on CMPIN_TR pin. However under light load both TREG and PP_THERMAL can be both disabled (CMPIN_TR_SELECT=1b & EN_TREG=0b & PP_THERMAL=0b), then device will keep CMPOUT pin high impedance to reduce quiescent current flow through voltage divider network.

BQ25773 Recommended Configuration for CMPIN_TR Temperature Regulation Figure 7-5 Recommended Configuration for CMPIN_TR Temperature Regulation

The target temperature regulation value can be chosen through configuring RS fixed resistor. A 10k NTC thermistor(ERTJ0EG103FA) is recommended in this application, corresponding RS fixed value can be calculated through equation below. The RS corresponding value at 60ºC/80ºC/100ºC TREG refers to Table 7-4. The corresponding CMPIN_TR pin voltage with swept temperature under 60ºC/80ºC/100ºC TREG configuration can be found in Figure 7-6. Based on this graph, besides temperature regulation function, the NTC temperature can also be measured through CMPIN_TR pin voltage. The device has a dedicated CMPIN_TR pin voltage ADC channel which can be enabled through setting EN_ADC_CMPIN=1b.

There is a dedicated PROCHOT profile in case regulation target gets overheat more than TREG target. The profile can enabled through setting PP_THERMAL=1b referring to Figure 7-10.

Equation 1. RS=5V-1.2V1.2V*RNTC@TREG
Table 7-4 CMPIN_TR Pin RC Network Configuration Reference Based on ERTJ0EG103FA NTC
RS TREG TEMPERATURE
9.53kΩ 60ºC
5.23kΩ 80ºC
3.01kΩ 100ºC
BQ25773 CMPIN_TR Pin Voltage vs Temperature Under Different Regulation Target (60°C/80°C/100°C) Figure 7-6 CMPIN_TR Pin Voltage vs Temperature Under Different Regulation Target (60°C/80°C/100°C)