The device powers up from the higher voltage of VBUS or VBAT through internal power selector. The charger starts up when VBUS exceeds V_{VBUS_UVLOZ} or VBAT exceeds V_{VBAT_UVLOZ} for 5ms. Upon POR(power on reset) the charger resets all the registers to the default state. Another 5 ms later, the user registers become accessible to the host. When VBAT> VBAT_UVLO: if VBUS falls below VBUS_UVLO then adapter removal is detected to enter battery only low power mode. When VBAT< VBAT_UVLO: if VBUS falls below VBUS_UVLO then device is off without I2C communication and device will POR when VBUS rise above VBUS_UVLOZ.

Power up sequence when the charger is powered up from VBUS:

• After VBUS rises above V_{VBUS_UVLOZ}, there is 50ms deglitch time. After this 50ms deglitch time, charger enables REGN_A/B LDOs. CHRG_OK pin goes high and STAT_AC is set to 1b once REGN_A/B voltages ramp up. (If EN_LWPWR set to 0b then device will be in performance mode, REGN_A/B will be kept on there is a battery present before VBUS is plugged in)
• MODE pin detection is executed after device POR to determine converter topology, converter compensation option and converter switching frequency.
• VBUS qualification is then executed. During VBUS qualification process, there is a internal 20mA current sink 100ms pulse adding on VBUS pin to make sure the input source is strong enough to pass qualification. During this 100ms if V_{VBUS_CONVEN}<VBUS <V_{ACOV_RISE}, then charger passes VBUS qualification and proceeds to the next step. However, if V_{VBUS_UVLOZ} < VBUS < V_{VBUS_CONVEN} or VBUS> V_{ACOV_RISE} then charger fails VBUS qualification, the charger will re-qualify VBUS every 2 s. During this 2 s, even if VBUS rise up higher than V_{VBUS_CONVEN,} the converter is still shutting down due to failing VBUS qualification at the beginning.
• During VBUS qualification, Battery cell configuration is read at CELL_BATPRES pin voltage and compared to REGN_A/B to determine cell configuration. The default value of CHARGE_VOLTAGE(), CHARGE_CURRENT(),VRECHG(), VSYS_MIN() and SYSOVP thresholds are loaded respectively. Also IINDPM is detected at ILIM_HIZ pin steady state voltage.
• After passing the qualification, VBUS ADC is executed one time to read the no-load VBUS voltage and save the value into ADC_VBUS() register.
• Check voltage between VBUS and ACP_A (VBUS-ACP_A) is below V_{SC_VBUSACP_FALLING} to make sure eFuse or PFETs are fully turned on. If not, hold on converter power up until SC_VBUSACP is not triggered.
• Normally 226 ms after VBUS above V_{VBUS_CONVEN}, converter powers up. If SC_VBUSACP keeps triggered then converter power up could wait until it is cleared.

Power up sequence when the charger is powered up from VBAT:

• If only battery is present and the voltage is above V_{VBAT_UVLOZ} , charger wakes up and the BATFET is turned on and connecting the battery to system.
• MODE pin detection is executed right after device POR to determine converter topology, converter compensation option and converter switching frequency.
• By default, the charger is in low power mode (EN_LWPWR = 1b) with lowest quiescent current. The REGN_A/B LDO is turned off by default but when EN_LWPWR=1, the LDO is turned on, the LDO current limit is reduced to 5mA in order to minimize the quiescent current.
• The adapter present comparator is activated, to monitor the VBUS voltage.
• SDA and SDL lines stand by waiting for host commands.
• Device can move to performance mode by configuring EN_LWPWR = 0b. The host can enable IBAT buffer through setting EN_IBAT=1b to monitor discharge current. The PSYS also can be enabled by the host. CELL_BATPRES pin detection is executed one time when CELL_BATPRES pin is pulled up or REGN_A/B rise up from GND to steady state value. Note under battery only low power mode, CELL_BATPRES detection is not executed.
• In performance mode, the REGN_A/B LDO is always available to provide an accurate reference and gate drive voltage for the converter.