SLUSEK7 September   2024 BQ25773

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics BQ2577X
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequence
      2. 7.3.2  MODE Pin Detection
      3. 7.3.3  REGN Regulator (REGN LDO)
      4. 7.3.4  Independent Comparator Function
      5. 7.3.5  Battery Charging Management
        1. 7.3.5.1 Autonomous Charging Cycle
        2. 7.3.5.2 Battery Charging Profile
        3. 7.3.5.3 Charging Termination
        4. 7.3.5.4 Charging Safety Timer
      6. 7.3.6  Temperature Regulation (TREG)
      7. 7.3.7  Vmin Active Protection (VAP) When Battery Only Mode
      8. 7.3.8  Two Level Battery Discharge Current Limit
      9. 7.3.9  Fast Role Swap Feature
      10. 7.3.10 CHRG_OK Indicator
      11. 7.3.11 Input and Charge Current Sensing
      12. 7.3.12 Input Current and Voltage Limit Setup
      13. 7.3.13 Battery Cell Configuration
      14. 7.3.14 Device HIZ State
      15. 7.3.15 USB On-The-Go (OTG)
      16. 7.3.16 Quasi Dual Phase Converter Operation
      17. 7.3.17 Continuous Conduction Mode (CCM)
      18. 7.3.18 Pulse Frequency Modulation (PFM)
      19. 7.3.19 Switching Frequency and Dithering Feature
      20. 7.3.20 Current and Power Monitor
        1. 7.3.20.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 7.3.20.2 High-Accuracy Power Sense Amplifier (PSYS)
      21. 7.3.21 Input Source Dynamic Power Management
      22. 7.3.22 Integrated 16-Bit ADC for Monitoring
      23. 7.3.23 Input Current Optimizer (ICO)
      24. 7.3.24 Two-Level Adapter Current Limit (Peak Power Mode)
      25. 7.3.25 Processor Hot Indication
        1. 7.3.25.1 PROCHOT During Low Power Mode
        2. 7.3.25.2 PROCHOT Status
      26. 7.3.26 Device Protection
        1. 7.3.26.1  Watchdog Timer (WD)
        2. 7.3.26.2  Input Overvoltage Protection (ACOV)
        3. 7.3.26.3  Input Overcurrent Protection (ACOC)
        4. 7.3.26.4  System Overvoltage Protection (SYSOVP)
        5. 7.3.26.5  Battery Overvoltage Protection (BATOVP)
        6. 7.3.26.6  Battery Charge Overcurrent Protection (BATCOC)
        7. 7.3.26.7  Battery Discharge Overcurrent Protection (BATDOC)
        8. 7.3.26.8  BATFET Charge Current Clamp Protection under LDO Regulation Mode
        9. 7.3.26.9  Sleep Comparator Protection Between VBUS and ACP_A (SC_VBUSACP)
        10. 7.3.26.10 High Duty Buck Exit Comparator Protection (HDBCP)
        11. 7.3.26.11 REGN Power Good Protection (REGN_PG)
        12. 7.3.26.12 System Under Voltage Lockout (VSYS_UVP) and Hiccup Mode
        13. 7.3.26.13 OTG Mode Over Voltage Protection (OTG_OVP)
        14. 7.3.26.14 OTG Mode Under Voltage Protection (OTG_UVP)
        15. 7.3.26.15 Thermal Shutdown (TSHUT)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forward Mode
        1. 7.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 7.4.1.2 Battery Charging
      2. 7.4.2 USB On-The-Go Mode
      3. 7.4.3 Pass Through Mode (PTM)-Patented Technology
      4. 7.4.4 Learn Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
        1. 7.5.1.1 Timing Diagrams
        2. 7.5.1.2 Data Validity
        3. 7.5.1.3 START and STOP Conditions
        4. 7.5.1.4 Byte Format
        5. 7.5.1.5 Acknowledge (ACK) and Not Acknowledge (NACK)
        6. 7.5.1.6 Target Address and Data Direction Bit
        7. 7.5.1.7 Single Read and Write
        8. 7.5.1.8 Multi-Read and Multi-Write
        9. 7.5.1.9 Write 2-Byte I2C Commands
    6. 7.6 BQ25773 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Snubber and Filter for Voltage Spike Damping
        2. 8.2.2.2 ACP-ACN Input Filter
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Power MOSFETs Selection
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Layout Example Reference Top View
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • REE|36
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.6 Power MOSFETs Selection

Six external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are integrated into the IC with 5 V of gate drive voltage. MOSFET breakdown voltage (BVDSS) rating refers to Table 8-7 based on different input voltage and application position. 5mm*6mm package MOSFET is preferred for better thermal performance and 3.3mm*3.3mm package MOSFET is preferred for higher power density design.

Table 8-7 MOSFET Voltage Rating Recommendation
20 V/100 W 28 V/140 W 36 V/180 W
Buck Half bridge (Q1_A,Q2_A,Q1_B,Q2_B) BVDSS=30 V or higher BVDSS=40 V or higher BVDSS=60 V or higher
Boost Half bridge (Q3,Q4) and BATFET (Q5) BVDSS=30 V or higher BVDSS=30 V or higher BVDSS=40 V or higher (for Buck HS short fault condition safety)

Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction loss and switching loss. For the top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance, RDS(ON), and the gate-to-drain charge, QGD. For the bottom side MOSFET, FOM is defined as the product of the MOSFET's on-resistance, RDS(ON), and the total gate charge, QG.

Equation 6. FOMtop = RDS(on) · QGD; FOMbottom = RDS(on) · QG

The lower the FOM value, the lower the total power loss. Usually lower RDS(ON) has higher cost with the same package size.

The top-side MOSFET loss includes conduction loss and switching loss. Taking buck mode operation as an example the power loss is a function of duty cycle (D=VOUT/VIN), charging current (ICHG), MOSFET's on-resistance (RDS(ON)_top), input voltage (VIN), switching frequency (fS), turn-on time (ton) and turn-off time (toff):

Equation 7. Ptop =Pcon_top+Psw_top
Equation 8. Pcon_top =D · IL_RMS2 · RDS(on)_top;
Equation 9. IL_RMS2=IL_DC2+Iripple2/12
  • IL_DC is the average inductor DC current under buck mode;
  • Iripple is the inductor current ripple peak-to-peak value;
Equation 10. Psw_top =PIV_top+PQoss_top+PGate_top;

The first item Pcon_top represents the conduction loss which is straight forward. The second term Psw_top represents the multiple switching loss items in top MOSFET including voltage and current overlap losses (PIV_top), MOSFET parasitic output capacitance loss (PQoss_top) and gate drive loss (PGate_top). To calculate voltage and current overlap losses (PIV_top):

Equation 11. PIV_top =0.5x VIN · Ivalley · ton· fS+0.5x VIN · Ipeak · toff · fS
Equation 12. Ivalley =IL_DC- 0.5 · Iripple (inductor current valley value);
Equation 13. Ipeak =IL_DC+ 0.5 · Iripple (inductor current peak value);
  • ton is the MOSFET turn-on time that VDS falling time from VIN to almost zero (MOSFET turn on conduction voltage);
  • toff is the MOSFET turn-off time that IDS falling time from Ipeak to zero;

The MOSFET turn-on and turn-off times are given by:

Equation 14. BQ25773

where Qsw is the switching charge, Ion is the turn-on gate driving current, and Ioff is the turn-off gate driving current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge (QGD) and gate-to-source charge (QGS):

Equation 15. Qsw =QGD+QGS

Gate driving current can be estimated by REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total turn-on gate resistance (Ron), and turn-off gate resistance (Roff) of the gate driver:

Equation 16. BQ25773

To calculate top MOSFET parasitic output capacitance loss (PQoss_top):

Equation 17. PQoss_top =0.5 · VIN· Qoss · fS
  • Qoss is the MOSFET parasitic output charge which can be found in MOSFET data sheet;

To calculate top MOSFET gate drive loss (PGate_top):

Equation 18. PGate_top =VIN· QGate_top · fS
  • QGate_top is the top MOSFET gate charge which can be found in MOSFET data sheet;
  • Note here VIN is used instead of real gate drive voltage 6 V because, the gate drive 6 V is generated based on LDO from VIN under buck mode, the total gate drive related loss are all considered when VIN is used for gate drive loss calculation .

The bottom-side MOSFET loss also includes conduction loss and switching loss:

Equation 19. Pbottom =Pcon_bottom+Psw_bottom
Equation 20. Pcon_bottom =(1 - D) · IL_RMS2 · RDS(on)_bottom;
Equation 21. Psw_bottom =PRR_bottom+PDead_bottom+PGate_bottom;

The first item Pcon_bottom represents the conduction loss which is straight forward. The second term Psw_bottom represents the multiple switching loss items in bottom MOSFET including reverse recovery losses (PRR_bottom), Dead time body diode conduction loss (PDead_bottom) and gate drive loss (PGate_bottom). The detail calculation can be found below:

Equation 22. PRR_bottom=VIN · Qrr · fS
  • Qrr is the bottom MOSFET reverse recovery charge which can be found in MOSFET data sheet;
Equation 23. PDead_bottom=VF · Ivalley · fS · tdead_rise+VF · Ipeak · fS · tdead_fall
  • VF is the body diode forward conduction voltage drop;
  • tdead_rise is the SW rising edge deadtime between top and bottom MOSFETs which is around 20 ns;
  • tdead_fall is the SW falling edge deadtime between top and bottom MOSFETs which is around 20 ns;

PGate_bottom can follow the same method as top MOSFET gate drive loss calculation approach refer to Equation 18.

N-channel MOSFETs is used for battery charging BATFET. The gate drivers are internally integrated into the IC with 5V of gate drive voltage. 30 V or higher voltage rating MOSFETs are preferred , the Ciss of N-channel MOSFET should be chosen less than 6 nF.